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Fixed fgen4

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This commit is contained in:
cturek 2022-09-20 20:00:01 +00:00
parent 11fb39b373
commit c3c764f0ba
2 changed files with 3 additions and 3 deletions
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4
pipelined/config/shared/wally-shared.vh
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@ -102,8 +102,8 @@
`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6)) `define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
// division constants // division constants
`define RADIX 32'h2 `define RADIX 32'h4
`define DIVCOPIES 32'h3 `define DIVCOPIES 32'h1
`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3)) `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
`define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input `define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input

2
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
View File

@ -49,7 +49,7 @@ module fdivsqrtfgen4 (
always_comb always_comb
if (u[3]) F = F2; if (u[3]) F = F2;
else if (u[2]) F = F1; else if (u[2]) F = F1;
else if (U[1]) F = FN1; else if (u[1]) F = FN1;
else if (u[0]) F = FN2; else if (u[0]) F = FN2;
else F = F0; else F = F0;
endmodule endmodule