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https://github.com/openhwgroup/cvw
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Removed mux in PCNextF logic. Minor IFU improvements.
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23c4ba2777
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@ -96,7 +96,6 @@ module ifu (
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logic [`XLEN-1:0] PCD;
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logic [`XLEN-1:0] PCD;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic reset_q; // see comment below about PCNextF and icache.
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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logic BPPredWrongM;
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logic BPPredWrongM;
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@ -106,8 +105,8 @@ module ifu (
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logic [`XLEN+1:0] PCFExt;
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logic [`XLEN+1:0] PCFExt;
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logic CacheableF;
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logic CacheableF;
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logic [`XLEN-1:0] PCNextFMux;
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logic [`XLEN-1:0] PCNextFSpill;
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logic [`XLEN-1:0] PCFMux;
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logic [`XLEN-1:0] PCFSpill;
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logic SelNextSpill;
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logic SelNextSpill;
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logic ICacheFetchLine;
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logic ICacheFetchLine;
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logic BusStall;
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logic BusStall;
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@ -127,8 +126,8 @@ module ifu (
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// this exists only if there are compressed instructions.
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// this exists only if there are compressed instructions.
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assign PCFp2 = PCF + `XLEN'b10;
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assign PCFp2 = PCF + `XLEN'b10;
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assign PCNextFMux = SelNextSpill ? PCFp2 : PCNextF;
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assign PCNextFSpill = SelNextSpill ? PCFp2 : PCNextF;
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assign PCFMux = SelSpill ? PCFp2 : PCF;
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assign PCFSpill = SelSpill ? PCFp2 : PCF;
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assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
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assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
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@ -167,18 +166,18 @@ module ifu (
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// end of spill support
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// end of spill support
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end else begin : NoSpillSupport // line: SpillSupport
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end else begin : NoSpillSupport // line: SpillSupport
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assign PCNextFMux = PCNextF;
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assign PCNextFSpill = PCNextF;
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assign PCFMux = PCF;
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assign PCFSpill = PCF;
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assign SelNextSpill = 0;
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assign SelNextSpill = 0;
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assign PostSpillInstrRawF = InstrRawF;
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assign PostSpillInstrRawF = InstrRawF;
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end
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end
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assign PCFExt = {2'b00, PCFMux};
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assign PCFExt = {2'b00, PCFSpill};
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mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
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mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
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immu(.PAdr(PCFExt[`PA_BITS-1:0]),
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immu(.PAdr(PCFExt[`PA_BITS-1:0]),
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.VAdr(PCFMux),
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.VAdr(PCFSpill),
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.Size(2'b10),
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.Size(2'b10),
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.PTE(PTE),
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.PTE(PTE),
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.PageTypeWriteVal(PageType),
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.PageTypeWriteVal(PageType),
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@ -235,7 +234,7 @@ module ifu (
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simpleram #(
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simpleram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.clk,
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.clk,
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.a(CPUBusy | reset ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
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.a(CPUBusy | reset ? PCPF[31:0] : PCNextFSpill[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
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.we(1'b0),
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.we(1'b0),
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.wd(0), .rd(FinalInstrRawF_FIXME));
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.wd(0), .rd(FinalInstrRawF_FIXME));
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assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
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assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
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@ -286,7 +285,7 @@ module ifu (
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.RW(IFURWF),
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.RW(IFURWF),
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.Atomic(2'b00),
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.Atomic(2'b00),
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.FlushCache(1'b0),
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.FlushCache(1'b0),
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.NextAdr(PCNextFMux[11:0]),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.PAdr(PCPF),
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.CacheCommitted(),
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.CacheCommitted(),
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.InvalidateCacheM(InvalidateICacheM));
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.InvalidateCacheM(InvalidateICacheM));
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@ -303,7 +302,7 @@ module ifu (
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// branch predictor signal
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// branch predictor signal
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logic SelBPPredF;
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
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logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F;
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logic [4:0] InstrClassD, InstrClassE;
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logic [4:0] InstrClassD, InstrClassE;
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@ -333,13 +332,7 @@ module ifu (
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
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// Mux only required on instruction class miss prediction.
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(PCNext3F));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
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// This mux is required as PCNextF needs to be the valid reset vector during reset.
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// Reseting PCF does not accomplish this as PCNextF will be +2/4 more than PCF.
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//mux2 #(`XLEN) pcmux4(.d0(PCNext3F), .d1(`RESET_VECTOR), .s(`MEM_IROM ? reset : reset_q), .y(UnalignedPCNextF));
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// mux2 #(`XLEN) pcmux4(.d0(PCNext3F), .d1(`RESET_VECTOR), .s(reset), .y(UnalignedPCNextF)); // ******* probably can get rid of by making reset SelAdr = 01
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assign UnalignedPCNextF = PCNext3F;
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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