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added delays to uart AHB signals

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bbracker 2021-03-22 15:40:29 -04:00
parent 7350b9f18f
commit c3a6d6bf42
1 changed files with 4 additions and 5 deletions
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9
wally-pipelined/src/uncore/uart.sv
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@ -45,11 +45,10 @@ module uart (
logic [7:0] Din, Dout; logic [7:0] Din, Dout;
// rename processor interface signals to match PC16550D and provide one-byte interface // rename processor interface signals to match PC16550D and provide one-byte interface
always_ff @(posedge HCLK) begin flopr #(1) memreadreg(HCLK, ~HRESETn, ~(HSELUART & ~HWRITE), MEMRb);
MEMRb <= ~(HSELUART & ~HWRITE); flopr #(1) memwritereg(HCLK, ~HRESETn, ~(HSELUART & HWRITE), MEMWb);
MEMWb <= ~(HSELUART & HWRITE); flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A);
A <= HADDR[2:0];
end
assign HRESPUART = 0; // OK assign HRESPUART = 0; // OK
assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something