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Remove verilator hack

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This commit is contained in:
Jordan Carlin 2024-06-26 22:39:43 -07:00
parent b0f5fbe497
commit c33ad35b75
1 changed files with 1 additions and 12 deletions
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testbench/testbench.sv
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@ -385,14 +385,6 @@ module testbench;
// and initialize them to zero (also initilaize them to zero at the start of the next test) // and initialize them to zero (also initilaize them to zero at the start of the next test)
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end end
`ifdef VERILATOR // this macro is defined when verilator is used
// Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is
// in the posedge clk block rather than a separate posedge Validate block.
// Until it is fixed, provide a silly posedge Validate block to keep Verilator happy.
// https://github.com/verilator/verilator/issues/4967
end // restored
always @(posedge Validate) // added
`endif
if(Validate) begin if(Validate) begin
if (PrevPCZero) totalerrors = totalerrors + 1; // error if PC is stuck at zero if (PrevPCZero) totalerrors = totalerrors + 1; // error if PC is stuck at zero
if (TEST == "buildroot") if (TEST == "buildroot")
@ -445,10 +437,7 @@ module testbench;
`endif `endif
end end
end end
`ifndef VERILATOR
// Remove this when issue 4967 is resolved and the posedge Validate logic above is removed
end end
`endif
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////