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Cleaned up ahbcacheinterface.

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This commit is contained in:
Ross Thompson 2023-01-17 22:13:56 -06:00
parent 4720b28272
commit c3096eea2a
3 changed files with 4 additions and 4 deletions
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4
pipelined/src/ebu/ahbcacheinterface.sv
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@ -30,7 +30,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHBW, CACHE_ENABLED) ( module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHBW) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface // bus interface
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
@ -67,7 +67,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHB
output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; localparam integer BeatCountThreshold = BEATSPERLINE - 1; //
logic [`PA_BITS-1:0] LocalHADDR; logic [`PA_BITS-1:0] LocalHADDR;
logic [LOGWPL-1:0] BeatCountDelayed; logic [LOGWPL-1:0] BeatCountDelayed;
logic CaptureEn; logic CaptureEn;

2
pipelined/src/ifu/ifu.sv
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@ -227,7 +227,7 @@ module ifu (
.NextAdr(PCNextFSpill[11:0]), .NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF), .PAdr(PCPF),
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, LLENPOVERAHBW, `ICACHE) ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, LLENPOVERAHBW)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),

2
pipelined/src/lsu/lsu.sv
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@ -272,7 +272,7 @@ module lsu (
.FetchBuffer, .CacheBusRW, .FetchBuffer, .CacheBusRW,
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .LLENPOVERAHBW(LLENPOVERAHBW), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),