mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
commit
c2f81e309b
@ -110,6 +110,15 @@ for test in tests32e:
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grepstr="All tests ran without failures")
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grepstr="All tests ran without failures")
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configs.append(tc)
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configs.append(tc)
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ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")]
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for test in ahbTests:
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tc = TestCase(
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name="ram_latency_" + test[0] + "_burst_en_" + test[1],
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variant="ahb",
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cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
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grepstr="All tests ran without failures")
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configs.append(tc)
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import os
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import os
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from multiprocessing import Pool, TimeoutError
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from multiprocessing import Pool, TimeoutError
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@ -20,11 +20,17 @@
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onbreak {resume}
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onbreak {resume}
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# create library
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# create library
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if {$2 eq "ahb"} {
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if [file exists wkdir/work_${1}_${2}_${3}_${4}] {
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vdel -lib wkdir/work_${1}_${2}_${3}_${4} -all
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}
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vlib wkdir/work_${1}_${2}_${3}_${4}
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} else {
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if [file exists wkdir/work_${1}_${2}] {
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if [file exists wkdir/work_${1}_${2}] {
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vdel -lib wkdir/work_${1}_${2} -all
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vdel -lib wkdir/work_${1}_${2} -all
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}
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}
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vlib wkdir/work_${1}_${2}
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vlib wkdir/work_${1}_${2}
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}
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# compile source files
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# compile source files
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# suppress spurious warnngs about
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# "Extra checking for conflicts with always_comb done at vopt time"
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@ -55,6 +61,20 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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run -all
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run -all
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exec ./slack-notifier/slack-notifier.py
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "ahb"} {
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vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt -fatal 7
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# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
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#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
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#vsim -coverage -lib work_$2 workopt_$2
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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run -all
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# power off -r /dut/core/*
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} else {
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} else {
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
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# start and run simulation
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# start and run simulation
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@ -75,8 +75,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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add log -r /*
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add log -r /*
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run 20 ms
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run 20 ms
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} else {
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if {$2 eq "ahb"} {
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
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} else {
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} else {
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
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}
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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vsim workopt +nowarn3829 -fatal 7
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@ -104,6 +104,7 @@ logic [3:0] dummy;
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"wally64periph": tests = wally64periph;
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"wally64periph": tests = wally64periph;
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"coremark": tests = coremark;
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"coremark": tests = coremark;
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"fpga": tests = fpga;
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"fpga": tests = fpga;
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"ahb" : tests = ahb;
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endcase
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endcase
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end else begin // RV32
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end else begin // RV32
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case (TEST)
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case (TEST)
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@ -1917,3 +1917,8 @@ string imperas32f[] = '{
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`WALLYTEST,
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`WALLYTEST,
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"NULL"
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"NULL"
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};
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};
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string ahb[] = '{
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`RISCVARCHTEST,
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"rv64i_m/F/src/fadd_b11-01.S"
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};
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