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Get non-jump case working

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This commit is contained in:
Jarred Allen 2021-03-14 14:46:21 -04:00
parent b30ea396b8
commit c2f2caa3f6
2 changed files with 8 additions and 4 deletions
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3
wally-pipelined/regression/wally-pipelined.do
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@ -74,6 +74,9 @@ add wave /testbench/InstrDName
add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD
add wave /testbench/dut/hart/ifu/ic/DelayF add wave /testbench/dut/hart/ifu/ic/DelayF
add wave /testbench/dut/hart/ifu/ic/DelaySideF
add wave /testbench/dut/hart/ifu/ic/DelayD
add wave /testbench/dut/hart/ifu/ic/DelaySideD
add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD
add wave -divider add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCE add wave -hex /testbench/dut/hart/ifu/PCE

9
wally-pipelined/src/ifu/icache.sv
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@ -40,7 +40,7 @@ module icache(
output logic [31:0] InstrRawD output logic [31:0] InstrRawD
); );
logic DelayF, DelaySideF, FlushDLastCycle; logic DelayF, DelaySideF, FlushDLastCycle, DelayD, DelaySideD;
logic [1:0] InstrDMuxChoice; logic [1:0] InstrDMuxChoice;
logic [15:0] MisalignedHalfInstrF, MisalignedHalfInstrD; logic [15:0] MisalignedHalfInstrF, MisalignedHalfInstrD;
logic [31:0] InstrF, AlignedInstrD; logic [31:0] InstrF, AlignedInstrD;
@ -49,7 +49,9 @@ module icache(
logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF; logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF;
flopr #(1) flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle); flopr #(1) flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle);
flopenr #(1) delayStateFlop(clk, reset, ~StallF, (DelayF & ~DelaySideF) ? 1'b1 : 1'b0 , DelaySideF); flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF, DelayD);
flopenr #(1) delaySideDFlop(clk, reset, ~StallF, DelaySideF, DelaySideD);
flopenr #(1) delayStateFlop(clk, reset, ~StallF, DelayF & ~DelaySideF, DelaySideF);
flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD); flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD);
// This flop is here to simulate pulling data out of the cache, which is edge-triggered // This flop is here to simulate pulling data out of the cache, which is edge-triggered
@ -99,7 +101,6 @@ module icache(
assign ICacheStallF = 0; //DelayF & ~DelaySideF; assign ICacheStallF = 0; //DelayF & ~DelaySideF;
// Detect if the instruction is compressed // Detect if the instruction is compressed
// TODO Low-hanging optimization, don't delay if getting a compressed instruction
assign CompressedF = (DelaySideF & DelayF) ? (MisalignedHalfInstrD[1:0] != 2'b11) : (InstrF[1:0] != 2'b11); assign CompressedF = (DelaySideF & DelayF) ? (MisalignedHalfInstrD[1:0] != 2'b11) : (InstrF[1:0] != 2'b11);
// Pick the correct output, depending on whether we have to assemble this // Pick the correct output, depending on whether we have to assemble this
@ -107,7 +108,7 @@ module icache(
// Output the requested instruction (we don't need to worry if the read is // Output the requested instruction (we don't need to worry if the read is
// incomplete, since the pipeline stalls for us when it isn't), or a NOP for // incomplete, since the pipeline stalls for us when it isn't), or a NOP for
// the cycle when the first of two reads comes in. // the cycle when the first of two reads comes in.
always_comb if (DelayF & (MisalignedHalfInstrF[1:0] != 2'b11)) begin always_comb if (DelayD & (MisalignedHalfInstrD[1:0] != 2'b11)) begin
assign InstrDMuxChoice = 2'b11; assign InstrDMuxChoice = 2'b11;
end else if (FlushDLastCycle) begin end else if (FlushDLastCycle) begin
assign InstrDMuxChoice = 2'b10; assign InstrDMuxChoice = 2'b10;