Major icache cleanup.

wally-pipelined/src/cache/icache.sv

@@ -49,7 +49,6 @@ module icache
    output logic 							ICacheStallF,
    input logic 								CacheableF,
    input logic 								ITLBMissF,
-   input logic 								ITLBWriteF,
    input logic 								InvalidateICacheM,
   
    // The raw (not decompressed) instruction that was requested
@@ -66,23 +65,18 @@ module icache
   localparam integer 		  INDEXLEN = $clog2(NUMLINES);
   localparam integer 		  TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
 
+  // *** not used?
   localparam WORDSPERLINE = BLOCKLEN/`XLEN;
   localparam LOGWPL = $clog2(WORDSPERLINE);
 
-  localparam integer 		  PA_WIDTH = `PA_BITS - 2;
   localparam integer 		  NUMWAYS = `ICACHE_NUMWAYS;
   
 
   // Input signals to cache memory
   logic 					  ICacheMemWriteEnable;
-  logic [`PA_BITS-1:0] 		  FinalPCPF;  
   // Output signals from cache memory
-  logic 					  ICacheReadEn;
   logic [BLOCKLEN-1:0] 		  ReadLineF;
-  
+  logic       				  SelAdr;
-
-
-  logic [1:0] 				  SelAdr;
   logic [INDEXLEN-1:0] 		  RAdr;
   logic [NUMWAYS-1:0] 		  VictimWay;
   logic 					  LRUWriteEn;
@@ -94,24 +88,20 @@ module icache
 
   logic [31:0] 				  ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0];
   
-  logic [`PA_BITS-1:0] 		  BasePAdrMaskedF;
-  logic [OFFSETLEN-1:0] 	  BasePAdrOffsetF;
-  
-  
   logic [NUMWAYS-1:0] 		  SRAMWayWriteEnable;
 
 
   mux2 #(INDEXLEN)
   AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 			.d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-			.s(SelAdr[0]),
+			.s(SelAdr),
 			.y(RAdr));
 
 
   cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
 			 .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
   MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
-					  .PAdr(FinalPCPF),
+					  .PAdr(PCPF),
 					  .WriteEnable(SRAMWayWriteEnable),
 					  .VDWriteEnable(1'b0),
 					  .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
@@ -131,7 +121,7 @@ module icache
       cachereplacementpolicy(.clk, .reset,
 							 .WayHit,
 							 .VictimWay,
-							 .LsuPAdrM(FinalPCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+							 .LsuPAdrM(PCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 							 .RAdr,
 							 .LRUWriteEn);
     end else begin:vict
@@ -154,19 +144,9 @@ module icache
 	assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
   endgenerate
 
-  assign FinalInstrRawF = ReadLineSetsF[FinalPCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
+  assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
-  
-  
-  assign FinalPCPF = PCPF;
 
-  // *** CHANGE ME
+  assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
-  // if not cacheable the offset bits needs to be sent to the EBU.
-  // if cacheable the offset bits are discarded.  $ FSM will fetch the whole block.
-  //assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
-  //assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
-  
-  //assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
-  assign ICacheBusAdr = {FinalPCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
   
   
   // truncate the offset from PCPF for memory address generation
@@ -177,11 +157,9 @@ module icache
   icachefsm  icachefsm(.clk,
 					   .reset,
 					   .CPUBusy,
-					   .ICacheReadEn,
 					   .ICacheMemWriteEnable,
 					   .ICacheStallF,
 					   .ITLBMissF,
-					   .ITLBWriteF,
 					   .IgnoreRequest,
 					   .ICacheBusAck,
 					   .ICacheFetchLine,

wally-pipelined/src/cache/icachefsm.sv

@@ -33,7 +33,6 @@ module icachefsm
 
    // inputs from mmu
    input logic 		  ITLBMissF,
-   input logic 		  ITLBWriteF,
 
    input logic 		  IgnoreRequest,
    input logic 		  CacheableF,
@@ -44,8 +43,6 @@ module icachefsm
    // icache internal inputs
    input logic 		  hit,
 
-   // icache internal outputs
-   output logic 	  ICacheReadEn,
    // Load data into the cache
    output logic 	  ICacheMemWriteEnable,
 
@@ -56,7 +53,7 @@ module icachefsm
    output logic 	  ICacheFetchLine,
 
    // icache internal outputs
-   output logic [1:0] SelAdr,
+   output logic       SelAdr,
    output logic 	  LRUWriteEn
    );
 
@@ -83,21 +80,19 @@ module icachefsm
   always_comb begin
     //IfuBusFetch = 1'b0;
     ICacheMemWriteEnable = 1'b0;
-    SelAdr = 2'b00;
+    SelAdr = 1'b0;
-    ICacheReadEn = 1'b0;
     ICacheStallF = 1'b1;
     LRUWriteEn = 1'b0;
     case (CurrState)
       STATE_READY: begin
-        SelAdr = 2'b00;
+        SelAdr = 1'b0;
-        ICacheReadEn = 1'b1;
 		if(IgnoreRequest) begin
-		  SelAdr = 2'b01;
+		  SelAdr = 1'b1;
 		  NextState = STATE_READY;
 		end else 
 		if(ITLBMissF) begin
 		  NextState = STATE_READY;
-		  SelAdr = 2'b01;
+		  SelAdr = 1'b1;
 		  ICacheStallF = 1'b0;
 		end
 		else if (CacheableF & hit) begin
@@ -105,17 +100,17 @@ module icachefsm
 		  LRUWriteEn = 1'b1;
 		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
-			SelAdr = 2'b01;
+			SelAdr = 1'b1;
 		  end else begin
             NextState = STATE_READY;
 		  end
         end else if (CacheableF & ~hit) begin
-		  SelAdr = 2'b01;                                         /// *********(
+		  SelAdr = 1'b1;                                         /// *********(
           NextState = STATE_MISS_FETCH_WDV;
         end else begin
 		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
-			SelAdr = 2'b01;
+			SelAdr = 1'b1;
 		  end else begin
             NextState = STATE_READY;
 		  end
@@ -123,7 +118,7 @@ module icachefsm
       end
       // branch 3 miss no spill
       STATE_MISS_FETCH_WDV: begin
-        SelAdr = 2'b01;
+        SelAdr = 1'b1;
         //IfuBusFetch = 1'b1;
         if (ICacheBusAck) begin
           NextState = STATE_MISS_FETCH_DONE;	  
@@ -132,24 +127,21 @@ module icachefsm
         end
       end
       STATE_MISS_FETCH_DONE: begin
-        SelAdr = 2'b01;
+        SelAdr = 1'b1;
         ICacheMemWriteEnable = 1'b1;
         NextState = STATE_MISS_READ;
       end
       STATE_MISS_READ: begin
-        SelAdr = 2'b01;
+        SelAdr = 1'b1;
-        ICacheReadEn = 1'b1;
         NextState = STATE_MISS_READ_DELAY;
       end
       STATE_MISS_READ_DELAY: begin
-        //SelAdr = 2'b01;
-        ICacheReadEn = 1'b1;
 		ICacheStallF = 1'b0;
 		LRUWriteEn = 1'b1;
 		if(CPUBusy) begin
-		  SelAdr = 2'b01;
+		  SelAdr = 1'b1;
 		  NextState = STATE_CPU_BUSY;
-		  SelAdr = 2'b01;
+		  SelAdr = 1'b1;
 		end else begin
           NextState = STATE_READY;
 		end
@@ -158,17 +150,16 @@ module icachefsm
 		ICacheStallF = 1'b0;
         if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY;
-		  SelAdr = 2'b01;
+		  SelAdr = 1'b1;
 		end
 		else begin
 		  NextState = STATE_READY;
 		end
       end
       default: begin
-        SelAdr = 2'b01;
+        SelAdr = 1'b1;
         NextState = STATE_READY;
       end
-      // *** add in error handling and invalidate/evict
     endcase
   end
 

wally-pipelined/src/ifu/ifu.sv

@@ -247,7 +247,7 @@ module ifu (
   generate
 	if(`MEM_ICACHE) begin : icache
 	  icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
-					.ICacheBusAdr, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, 
+					.ICacheBusAdr, .ICacheStallF, .ITLBMissF, .FinalInstrRawF, 
 					.ICacheFetchLine,
 					.CacheableF,
 					.PCNextF(PCNextFMux),