From c29a2ff8df2199d684b54cd7e91526a497b14b90 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 21:11:41 -0400 Subject: [PATCH] Started atomics --- wally-pipelined/config/rv32ic/wally-config.vh | 2 +- wally-pipelined/src/lsu/lsu.sv | 29 ++++--------------- .../testbench/testbench-imperas.sv | 16 +++++----- 3 files changed, 13 insertions(+), 34 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 090da8d62..8b63c56a5 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -33,7 +33,7 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0) `define ZCSR_SUPPORTED 1 `define COUNTERS 32 `define ZCOUNTERS_SUPPORTED 1 diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 86b7995d4..81257a72a 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -134,6 +134,7 @@ module lsu logic [`XLEN-1:0] MemAdrEtoDCache; logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; + logic MemReadM; logic SquashSCWfromDCache; logic DataMisalignedMfromDCache; logic HPTWReady; @@ -246,6 +247,10 @@ module lsu .AtomicAllowed(), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + assign MemReadM = MemRWMtoDCache[1]; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; + lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoDCache, .AtomicMtoDCache, .MemPAdrM, + .SquashSCM, .SquashSCWfromDCache); + // *** BUG, this is most likely wrong assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; @@ -288,30 +293,6 @@ module lsu assign CommittedMfromDCache = preCommittedM | CommitM; - // Handle atomic load reserved / store conditional - generate - if (`A_SUPPORTED) begin // atomic instructions supported - logic [`PA_BITS-1:2] ReservationPAdrW; - logic ReservationValidM, ReservationValidW; - logic lrM, scM, WriteAdrMatchM; - - assign lrM = MemReadM && AtomicMtoDCache[0]; - assign scM = MemRWMtoDCache[0] && AtomicMtoDCache[0]; - assign WriteAdrMatchM = MemRWMtoDCache[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; - assign SquashSCM = scM && ~WriteAdrMatchM; - always_comb begin // ReservationValidM (next value of valid reservation) - if (lrM) ReservationValidM = 1; // set valid on load reserve - else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc - else ReservationValidM = ReservationValidW; // otherwise don't change valid - end - flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid - flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCWfromDCache); - end else begin // Atomic operations not supported - assign SquashSCM = 0; - assign SquashSCWfromDCache = 0; - end - endgenerate -----/\----- EXCLUDED -----/\----- */ // Determine if address is valid diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 8559c5555..2ae8f72e4 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -152,7 +152,7 @@ string tests32f[] = '{ }; string tests64a[] = '{ - "rv64a/WALLY-AMO", "2110", + //"rv64a/WALLY-AMO", "2110", "rv64a/WALLY-LRSC", "2110" }; @@ -310,7 +310,7 @@ string tests32f[] = '{ }; string tests32a[] = '{ - "rv64a/WALLY-AMO", "2110", + //"rv64a/WALLY-AMO", "2110", "rv64a/WALLY-LRSC", "2110" }; @@ -534,10 +534,10 @@ string tests32f[] = '{ if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; + if (`A_SUPPORTED) tests = {tests64a, tests}; end //tests = {tests64a, tests}; end else begin // RV32 @@ -551,10 +551,10 @@ string tests32f[] = '{ if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; else tests = {tests, tests32iNOc}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; - //if (`A_SUPPORTED) tests = {tests, tests32a}; if (`F_SUPPORTED) tests = {tests32f, tests}; if (`MEM_VIRTMEM) tests = {tests32mmu, tests}; - end + if (`A_SUPPORTED) tests = {tests32a, tests}; + end end end @@ -669,10 +669,8 @@ string tests32f[] = '{ // report errors unless they are garbage at the end of the sim // kind of hacky test for garbage right now errors = errors+1; - $display(" Error on test %s result %d: adr = %h sim = %h, signature = %h", - tests[test], i, (testadr+i)*(`XLEN/8), dut.uncore.dtim.RAM[testadr+i], signature[i]); - $display(" Error on test %s result %d: adr = %h sim = %h, signature = %h", - tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]); + $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", + tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]); $stop;//***debug end end