diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index e554fa999..299db18f8 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -180,6 +180,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
+		.d2({VictimTag, FlushAdr, OFFSETLEN'b0}),
 		.s({SelFlush, SelEvict}),
 		.y(CacheBusAdr));