mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #194 from davidharrishmc/dev
Bit manipulation support in ImperasDV. Test improvements.
This commit is contained in:
commit
c21a5aaaf7
@ -18,7 +18,8 @@ all: riscoftests memfiles coveragetests
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coverage:
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coverage:
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#make -C ../tests/coverage --jobs
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#make -C ../tests/coverage --jobs
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#iter-elf.bash --cover --search ../tests/coverage
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#iter-elf.bash --cover --search ../tests/coverage
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vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log
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vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
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# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log
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vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
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vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
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vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
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vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
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vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt
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vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt
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@ -24,8 +24,12 @@
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#// and limitations under the License.
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#// and limitations under the License.
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#////////////////////////////////////////////////////////////////////////////////////////////////
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#////////////////////////////////////////////////////////////////////////////////////////////////
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# This file should be a last resort. It's preferable to put
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# // coverage off
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# statements inline with the code whenever possible.
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# LZA (i<64) statement confuses coverage tool
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# LZA (i<64) statement confuses coverage tool
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# This is ugly to exlcude the whole file - is there a better option
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# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working
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coverage exclude -srcfile lzc.sv
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coverage exclude -srcfile lzc.sv
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@ -6,14 +6,18 @@
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# Core settings
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# Core settings
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--override cpu/unaligned=F
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--override cpu/unaligned=F
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--override cpu/ignore_non_leaf_DAU=1
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--override cpu/ignore_non_leaf_DAU=1
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--override cpu/wfi_is_nop=T
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#--override cpu/wfi_is_nop=T
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--override cpu/mimpid=0x100
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--override cpu/mimpid=0x100
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--override cpu/misa_Extensions_mask=0x0
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--override cpu/misa_Extensions_mask=0x0
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# THIS NEEDS FIXING to 16
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--override cpu/PMP_registers=16
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--override cpu/PMP_registers=16
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--override cpu/PMP_undefined=T
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--override cpu/PMP_undefined=T
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# Wally-specific non-default configuraiton
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--override refRoot/cpu/Sstc=T
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--override cpu/add_implicit_Extensions=B
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--override cpu/bitmanip_version=1.0.0
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# Illegal instruction should not contain the bit pattern
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# Illegal instruction should not contain the bit pattern
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# illegal pmp read contained this
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# illegal pmp read contained this
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# --override cpu/tval_ii_code=F
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# --override cpu/tval_ii_code=F
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@ -47,9 +51,12 @@
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/extensions=RV32I
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#-override refRoot/cpu/cv/extensions=RV32I
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# Add Imperas simulator application instruction tracing
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# Add Imperas simulator application instruction tracing
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--override cpu/show_c_prefix=T
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--override cpu/show_c_prefix=T
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--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
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--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000
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# Exceptions and pagetables debug
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# Exceptions and pagetables debug
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--override cpu/debugflags=6
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--override cpu/debugflags=6
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@ -56,7 +56,12 @@ def getBuildrootTC(boot):
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BRgrepstr="WallyHostname login:"
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BRgrepstr="WallyHostname login:"
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else:
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else:
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name="buildroot"
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name="buildroot"
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
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if (coverage):
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print( "buildroot coverage")
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
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else:
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print( "buildroot no coverage")
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
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BRgrepstr=str(INSTR_LIMIT)+" instructions"
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BRgrepstr=str(INSTR_LIMIT)+" instructions"
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return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
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return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
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@ -130,14 +135,11 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z
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"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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if (coverage): # delete all but 64gc tests when running coverage
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if (coverage): # delete all but 64gc tests when running coverage
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configs = []
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configs = []
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# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
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# "arch64zi", "wally64a", "wally64periph", "wally64priv",
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# "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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# "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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coverStr = '-coverage'
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coverStr = '-coverage'
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else:
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else:
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coverStr = ''
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coverStr = ''
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@ -179,8 +181,6 @@ def main():
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try:
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try:
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os.chdir(regressionDir)
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os.chdir(regressionDir)
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os.mkdir("logs")
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os.mkdir("logs")
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#print(os.getcwd())
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#print(regressionDir)
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except:
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except:
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pass
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pass
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try:
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try:
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@ -201,9 +201,11 @@ def main():
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TIMEOUT_DUR = 30*7200 # seconds
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TIMEOUT_DUR = 30*7200 # seconds
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configs=[getBuildrootTC(boot=True)]
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configs=[getBuildrootTC(boot=True)]
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elif '-coverage' in sys.argv:
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elif '-coverage' in sys.argv:
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TIMEOUT_DUR = 20*60 # seconds
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TIMEOUT_DUR = 20*60 # seconds
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#configs.append(getBuildrootTC(boot=False))
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# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
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os.system('rm cov/*.ucdb')
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# Also it is slow to run.
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# configs.append(getBuildrootTC(boot=False))
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os.system('rm -f cov/*.ucdb')
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else:
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else:
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TIMEOUT_DUR = 10*60 # seconds
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TIMEOUT_DUR = 10*60 # seconds
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configs.append(getBuildrootTC(boot=False))
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configs.append(getBuildrootTC(boot=False))
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@ -225,12 +227,6 @@ def main():
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# Coverage report
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# Coverage report
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if coverage:
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if coverage:
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os.system('make coverage')
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os.system('make coverage')
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#print('Generating coverage report')
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#os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log')
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#os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt')
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#os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt')
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#os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt')
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#os.system('vcover report -details -threshH 100 -html cov/cov.ucdb')
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# Count the number of failures
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# Count the number of failures
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if num_fail:
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if num_fail:
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print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
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print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
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@ -46,7 +46,7 @@ mkdir -p cov
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# Check if measuring coverage
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# Check if measuring coverage
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set coverage 0
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set coverage 0
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if {$argc >= 3} {
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if {$argc >= 3} {
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if {$3 eq "-coverage"} {
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if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
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set coverage 1
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set coverage 1
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}
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}
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}
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}
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@ -61,8 +61,14 @@ if {$argc >= 3} {
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if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# start and run simulation
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
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if { $coverage } {
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vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7
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echo "wally-batch buildroot coverage"
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf
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vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover
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} else {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7
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}
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run -all
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run -all
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run -all
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run -all
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@ -139,6 +145,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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}
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}
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if {$coverage} {
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if {$coverage} {
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echo "Saving coverage to ${1}_${2}.ucdb"
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
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coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
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}
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}
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@ -88,7 +88,9 @@ module hazard (
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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// Stall each stage for cause or if the next stage is stalled
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// Stall each stage for cause or if the next stage is stalled
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// coverage off: StallFCause is always 0
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallF = StallFCause | StallD;
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// coverage on
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assign #1 StallD = StallDCause | StallE;
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assign #1 StallD = StallDCause | StallE;
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assign #1 StallE = StallECause | StallM;
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assign #1 StallE = StallECause | StallM;
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assign #1 StallM = StallMCause | StallW;
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assign #1 StallM = StallMCause | StallW;
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@ -99,8 +99,10 @@ module bmuctrl(
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
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else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
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17'b0110011_0000100_100: if (`XLEN == 32)
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// // coverage off: This case can't occur in RV64
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
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// 17'b0110011_0000100_100: if (`XLEN == 32)
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// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
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// // coverage on
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
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|
@ -263,7 +263,9 @@ module controller(
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end else assign sltD = (Funct3D == 3'b010);
|
end else assign sltD = (Funct3D == 3'b010);
|
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|
|
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// Combine base and bit manipulation signals
|
// Combine base and bit manipulation signals
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|
// coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
|
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assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
|
assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
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|
// coverage on
|
||||||
assign RegWriteD = BaseRegWriteD | BRegWriteD;
|
assign RegWriteD = BaseRegWriteD | BRegWriteD;
|
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assign W64D = BaseW64D | BW64D;
|
assign W64D = BaseW64D | BW64D;
|
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assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
|
assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
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||||||
|
@ -149,7 +149,7 @@ module lsu (
|
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// MMU include PMP and is needed if any privileged supported
|
// MMU include PMP and is needed if any privileged supported
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
|
if(`VIRTMEM_SUPPORTED) begin : hptw
|
||||||
hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
|
hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
|
||||||
.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
|
.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
|
||||||
.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
|
.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
|
||||||
|
@ -202,7 +202,7 @@ module csr #(parameter
|
|||||||
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
||||||
assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
|
assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
|
||||||
assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
|
assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
|
||||||
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
|
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
|
||||||
assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM;
|
assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM;
|
||||||
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
|
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
|
||||||
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
|
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
|
||||||
|
@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
|
CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
|
||||||
CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
|
CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
|
||||||
CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
|
CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
|
||||||
|
CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
|
||||||
// user CSRs
|
// user CSRs
|
||||||
CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
|
CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
|
||||||
CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
|
CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
|
||||||
@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
CSRArray[12'h143] = CSRArrayOld[12'h143];
|
CSRArray[12'h143] = CSRArrayOld[12'h143];
|
||||||
CSRArray[12'h142] = CSRArrayOld[12'h142];
|
CSRArray[12'h142] = CSRArrayOld[12'h142];
|
||||||
CSRArray[12'h144] = CSRArrayOld[12'h144];
|
CSRArray[12'h144] = CSRArrayOld[12'h144];
|
||||||
|
CSRArray[12'h14D] = CSRArrayOld[12'h14D];
|
||||||
// user CSRs
|
// user CSRs
|
||||||
CSRArray[12'h001] = CSRArrayOld[12'h001];
|
CSRArray[12'h001] = CSRArrayOld[12'h001];
|
||||||
CSRArray[12'h002] = CSRArrayOld[12'h002];
|
CSRArray[12'h002] = CSRArrayOld[12'h002];
|
||||||
@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
CSRArrayOld[12'h143] = CSRArray[12'h143];
|
CSRArrayOld[12'h143] = CSRArray[12'h143];
|
||||||
CSRArrayOld[12'h142] = CSRArray[12'h142];
|
CSRArrayOld[12'h142] = CSRArray[12'h142];
|
||||||
CSRArrayOld[12'h144] = CSRArray[12'h144];
|
CSRArrayOld[12'h144] = CSRArray[12'h144];
|
||||||
|
CSRArrayOld[12'h14D] = CSRArray[12'h14D];
|
||||||
// user CSRs
|
// user CSRs
|
||||||
CSRArrayOld[12'h001] = CSRArray[12'h001];
|
CSRArrayOld[12'h001] = CSRArray[12'h001];
|
||||||
CSRArrayOld[12'h002] = CSRArray[12'h002];
|
CSRArrayOld[12'h002] = CSRArray[12'h002];
|
||||||
@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
|
assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
|
||||||
assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
|
assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
|
||||||
assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
|
assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
|
||||||
|
assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
|
||||||
assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
|
assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
|
||||||
assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
|
assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
|
||||||
assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
|
assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
|
||||||
@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
|
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
|
||||||
assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
|
assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
|
||||||
assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
|
assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
|
||||||
|
assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
|
||||||
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
|
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
|
||||||
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
|
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
|
||||||
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
|
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
|
||||||
@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
|
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
|
||||||
assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
|
assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
|
||||||
assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
|
assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
|
||||||
|
assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D];
|
||||||
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
|
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
|
||||||
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
|
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
|
||||||
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
|
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
|
||||||
|
@ -28,6 +28,11 @@
|
|||||||
|
|
||||||
main:
|
main:
|
||||||
|
|
||||||
|
# Division test (having trouble with buildroot)
|
||||||
|
li x11, 0x384000
|
||||||
|
li x12, 0x1c2000
|
||||||
|
divuw x9, x11, x12
|
||||||
|
|
||||||
# Test clz with all bits being 0
|
# Test clz with all bits being 0
|
||||||
li t0, 0
|
li t0, 0
|
||||||
clz t1, t0
|
clz t1, t0
|
||||||
@ -61,5 +66,6 @@ main:
|
|||||||
.word 0x6080101B // Illegal BMU similar to count word
|
.word 0x6080101B // Illegal BMU similar to count word
|
||||||
.word 0x6030101B // Illegal BMU similar to count word
|
.word 0x6030101B // Illegal BMU similar to count word
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|
||||||
|
@ -36,12 +36,36 @@ main:
|
|||||||
addi t0, zero, 0
|
addi t0, zero, 0
|
||||||
csrr t0, stimecmp
|
csrr t0, stimecmp
|
||||||
|
|
||||||
|
|
||||||
|
# satp write with mstatus.TVM = 1
|
||||||
|
bseti t0, zero, 20
|
||||||
|
csrs mstatus, t0
|
||||||
|
csrw satp, zero
|
||||||
|
|
||||||
|
# STIMECMP from S mode
|
||||||
|
li t0, 1
|
||||||
|
ecall # enter S-mode
|
||||||
|
csrw stimecmp, zero
|
||||||
|
li t0, 3
|
||||||
|
ecall # return to M-mode
|
||||||
|
csrsi mcounteren, 2 # mcounteren_tm = 1
|
||||||
|
li t0, 1
|
||||||
|
ecall # supervisor mode again
|
||||||
|
csrw stimecmp, zero
|
||||||
|
li t0, 3
|
||||||
|
ecall # machine mode again
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
|
# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
|
||||||
li t0, 0
|
li t0, 0
|
||||||
csrw stval, t0
|
csrw stval, t0
|
||||||
csrw scause, t0
|
csrw scause, t0
|
||||||
csrw sepc, t0
|
csrw sepc, t0
|
||||||
csrw stimecmp, t0
|
csrw stimecmp, t0
|
||||||
|
csrw scounteren, zero
|
||||||
|
csrw satp, zero
|
||||||
|
|
||||||
|
|
||||||
# Switch to machine mode
|
# Switch to machine mode
|
||||||
li a0, 3
|
li a0, 3
|
||||||
|
Loading…
Reference in New Issue
Block a user