Merge pull request #194 from davidharrishmc/dev

Bit manipulation support in ImperasDV.  Test improvements.

sim/Makefile

@@ -18,7 +18,8 @@ all: riscoftests memfiles coveragetests
 coverage:
 	#make -C ../tests/coverage --jobs
 	#iter-elf.bash --cover --search ../tests/coverage
-	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log
+	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
+#	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log
 	vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt

sim/coverage-exclusions-rv64gc.do

@@ -24,8 +24,12 @@
 #// and limitations under the License.
 #////////////////////////////////////////////////////////////////////////////////////////////////
 
+# This file should be a last resort.  It's preferable to put 
+# // coverage off 
+# statements inline with the code whenever possible.
+
 # LZA (i<64) statement confuses coverage tool 
-# This is ugly to exlcude the whole file - is there a better option
+# This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
 coverage exclude -srcfile lzc.sv 
 
 

sim/imperas.ic

@@ -6,14 +6,18 @@
 # Core settings
 --override cpu/unaligned=F
 --override cpu/ignore_non_leaf_DAU=1
---override cpu/wfi_is_nop=T
+#--override cpu/wfi_is_nop=T
 --override cpu/mimpid=0x100
 --override cpu/misa_Extensions_mask=0x0
 
-# THIS NEEDS FIXING to 16
 --override cpu/PMP_registers=16
 --override cpu/PMP_undefined=T
 
+# Wally-specific non-default configuraiton
+--override refRoot/cpu/Sstc=T 
+--override cpu/add_implicit_Extensions=B 
+--override cpu/bitmanip_version=1.0.0
+
 # Illegal instruction should not contain the bit pattern
 # illegal pmp read contained this
 # --override cpu/tval_ii_code=F
@@ -47,9 +51,12 @@
 #-override  refRoot/cpu/cv/cover=basic
 #-override  refRoot/cpu/cv/extensions=RV32I
 
+
+
 # Add Imperas simulator application instruction tracing
 --override cpu/show_c_prefix=T
---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
+
+--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000
 
 # Exceptions and pagetables debug
 --override cpu/debugflags=6

sim/regression-wally

@@ -56,7 +56,12 @@ def getBuildrootTC(boot):
         BRgrepstr="WallyHostname login:"
     else:
         name="buildroot"
-        BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
+        if (coverage):
+            print( "buildroot coverage")
+            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
+        else:
+            print( "buildroot no coverage")
+            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
     return  TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
 
@@ -130,14 +135,11 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z
              "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
+#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
     tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", 
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
                  "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
                  "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
-#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
-#                 "arch64zi", "wally64a", "wally64periph", "wally64priv", 
-#                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
-#                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
     coverStr = '-coverage'
 else:
    coverStr = ''
@@ -179,8 +181,6 @@ def main():
     try:
         os.chdir(regressionDir)
         os.mkdir("logs")
-        #print(os.getcwd())
-        #print(regressionDir)
     except:
         pass
     try:
@@ -201,9 +201,11 @@ def main():
         TIMEOUT_DUR = 30*7200 # seconds
         configs=[getBuildrootTC(boot=True)]
     elif '-coverage' in sys.argv:
-        TIMEOUT_DUR = 20*60 # seconds       
+        TIMEOUT_DUR = 20*60 # seconds    
-        #configs.append(getBuildrootTC(boot=False))
+    #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
-        os.system('rm cov/*.ucdb')
+    #   Also it is slow to run.   
+    #    configs.append(getBuildrootTC(boot=False))
+        os.system('rm -f cov/*.ucdb')
     else:
         TIMEOUT_DUR = 10*60 # seconds
         configs.append(getBuildrootTC(boot=False))
@@ -225,12 +227,6 @@ def main():
     # Coverage report
     if coverage:
        os.system('make coverage')
-       #print('Generating coverage report')
-       #os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log')
-       #os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt')
-       #os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt')
-       #os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt')
-       #os.system('vcover report -details -threshH 100 -html cov/cov.ucdb')
     # Count the number of failures
     if num_fail:
         print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)

sim/wally-batch.do

@@ -46,7 +46,7 @@ mkdir -p cov
 # Check if measuring coverage
  set coverage 0
 if {$argc >= 3} {
-    if {$3 eq "-coverage"} {
+    if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
         set coverage 1
     }
 }
@@ -61,8 +61,14 @@ if {$argc >= 3} {
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+    if { $coverage } {
-    vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
+        echo "wally-batch buildroot coverage"
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf
+        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7 -cover
+     } else {
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
+    }
 
     run -all
     run -all
@@ -139,6 +145,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 } 
 
 if {$coverage} {
+    echo "Saving coverage to ${1}_${2}.ucdb"
     do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
     coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
 }

src/hazard/hazard.sv

@@ -88,7 +88,9 @@ module hazard (
   assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
 
   // Stall each stage for cause or if the next stage is stalled
+  // coverage off: StallFCause is always 0
   assign #1 StallF = StallFCause | StallD;
+  // coverage on
   assign #1 StallD = StallDCause | StallE;
   assign #1 StallE = StallECause | StallM;
   assign #1 StallM = StallMCause | StallW;

src/ieu/bmu/bmuctrl.sv

@@ -99,8 +99,10 @@ module bmuctrl(
                                   BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
                                 else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
                                   BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
-        17'b0110011_0000100_100: if (`XLEN == 32)
+//        // coverage off: This case can't occur in RV64
-                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        17'b0110011_0000100_100: if (`XLEN == 32)
+//                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        // coverage on
         17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
         17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
         17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor

src/ieu/controller.sv

@@ -263,7 +263,9 @@ module controller(
     end else assign sltD = (Funct3D == 3'b010);
 
     // Combine base and bit manipulation signals
+    // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
     assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
+    // coverage on
     assign RegWriteD = BaseRegWriteD | BRegWriteD; 
     assign W64D = BaseW64D | BW64D;
     assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;

src/lsu/lsu.sv

@@ -149,7 +149,7 @@ module lsu (
   // MMU include PMP and is needed if any privileged supported
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
+  if(`VIRTMEM_SUPPORTED) begin : hptw
     hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,

src/privileged/csr.sv

@@ -202,7 +202,7 @@ module csr #(parameter
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
   assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW)  & InstrValidNotFlushedM;
+  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
   assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;

testbench/common/wallyTracer.sv

@@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
 	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
 	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
 	  // user CSRs
 	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
 	  CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
@@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = CSRArrayOld[12'h143];
 	  CSRArray[12'h142] = CSRArrayOld[12'h142];
 	  CSRArray[12'h144] = CSRArrayOld[12'h144];
+	  CSRArray[12'h14D] = CSRArrayOld[12'h14D];
 	  // user CSRs
 	  CSRArray[12'h001] = CSRArrayOld[12'h001];
 	  CSRArray[12'h002] = CSRArrayOld[12'h002];
@@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h143] = CSRArray[12'h143];
     CSRArrayOld[12'h142] = CSRArray[12'h142];
     CSRArrayOld[12'h144] = CSRArray[12'h144];
+    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
     // user CSRs
     CSRArrayOld[12'h001] = CSRArray[12'h001];
     CSRArrayOld[12'h002] = CSRArray[12'h002];
@@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
   assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
   assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
+  assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
   assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
   assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
   assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
@@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
   assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
   assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
+  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
   assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
   assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
   assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
@@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
   assign rvvi.csr[0][0][12'h142]    = CSRArray[12'h142];
   assign rvvi.csr[0][0][12'h144]    = CSRArray[12'h144];
+  assign rvvi.csr[0][0][12'h14D]    = CSRArray[12'h14D];
   assign rvvi.csr[0][0][12'h001]    = CSRArray[12'h001];
   assign rvvi.csr[0][0][12'h002]    = CSRArray[12'h002];
   assign rvvi.csr[0][0][12'h003]    = CSRArray[12'h003];

tests/coverage/ieu.S

@@ -28,6 +28,11 @@
 
 main:
 
+    # Division test (having trouble with buildroot)
+    li x11, 0x384000
+    li x12, 0x1c2000
+    divuw x9, x11, x12
+
     # Test clz with all bits being 0
     li t0, 0
     clz t1, t0
@@ -61,5 +66,6 @@ main:
     .word 0x6080101B  // Illegal BMU similar to count word
     .word 0x6030101B  // Illegal BMU similar to count word
 
+
     j done
 

tests/coverage/priv.S

@@ -36,12 +36,36 @@ main:
     addi t0, zero, 0
     csrr t0, stimecmp 
 
+
+    # satp write with mstatus.TVM = 1
+    bseti t0, zero, 20 
+    csrs mstatus, t0
+    csrw satp, zero
+
+    # STIMECMP from S mode
+    li t0, 1
+    ecall   # enter S-mode
+    csrw stimecmp, zero
+    li t0, 3
+    ecall   # return to M-mode
+    csrsi mcounteren, 2 # mcounteren_tm = 1
+    li t0, 1
+    ecall   # supervisor mode again
+    csrw stimecmp, zero
+    li t0, 3
+    ecall  # machine mode again
+
+
+
     # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
     li t0, 0
     csrw stval, t0
     csrw scause, t0
     csrw sepc, t0
     csrw stimecmp, t0
+    csrw scounteren, zero
+    csrw satp, zero
+
 
     # Switch to machine mode
     li a0, 3