Merge pull request #45 from stineje/main

Update ram2 and other memories and associated wrappers

pipelined/src/generic/mem/ram2p1r1wbe.sv

@@ -6,6 +6,8 @@
 //          When clk rises Addr and LineWriteData are sampled.
 //          Following the clk edge read data is output from the sampled Addr.
 //          Write
+// Modified: james.stine@okstate.edu Feb 1, 2023
+//           Integration of memories 
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
@@ -43,11 +45,57 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 );
 
    logic [WIDTH-1:0] 		   mem[DEPTH-1:0];
+   localparam                      SRAMWIDTH = 32;
+   localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
 
   // ***************************************************************************
   // TRUE Smem macro
   // ***************************************************************************
 
+   if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin
+   
+      ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
+				  .CEBA(~ce1), .CEBB(~ce2),
+				  .WEBA('0), .WEBB(~we2),			      
+				  .AA(ra1), .AB(wa2),
+				  .DA('0),
+				  .DB(wd2),
+				  .BWEBA('0), .BWEBB('1),
+				  .QA(rd1),
+				  .QB());
+
+   end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
+
+      logic [SRAMWIDTH-1:0]     SRAMReadData;      
+      logic [SRAMWIDTH-1:0]     SRAMWriteData;      
+      logic [SRAMWIDTH-1:0]     RD1Sets[SRAMNUMSETS-1:0];
+      logic [SRAMNUMSETS-1:0] 	SRAMBitMaskPre;      
+      logic [SRAMWIDTH-1:0] 	SRAMBitMask;      
+      logic [$clog2(DEPTH)-1:0] RA1Q;
+      
+      
+      onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
+      genvar 		    index;
+      for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
+	 assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];	 
+	 assign SRAMWriteData[index*2+1:index*2] = wd2;
+	 assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};      
+      end
+      flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);      
+      assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
+      ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), 
+				.CEBA(~ce1), .CEBB(~ce2),
+				.WEBA('0), .WEBB(~we2),			      
+				.AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
+				.AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
+				.DA('0),
+				.DB(SRAMWriteData),
+				.BWEBA('0), .BWEBB(SRAMBitMask),
+				.QA(SRAMReadData),
+				.QB());
+
+   end else begin
+      
       // ***************************************************************************
       // READ first SRAM model
       // ***************************************************************************
@@ -69,4 +117,6 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
        if (ce2 & we2 & bwe2[WIDTH/8])
          mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
 
+  end
+   
 endmodule

pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// ram2p1rwbe_1024x69.sv
+// ram2p1rwbe_1024x68.sv
 //
 // Written: james.stine@okstate.edu 28 January 2023
 // Modified: 
@@ -24,7 +24,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ram2p1r1wbe_1024x69( 
+module ram2p1r1wbe_1024x68( 
   input  logic          CLKA, 
   input  logic          CLKB, 
   input  logic 	        CEBA, 
@@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69(
   input  logic          WEBB,
   input  logic [9:0]    AA, 
   input  logic [9:0]    AB, 
-  input  logic [68:0]   DA,
+  input  logic [67:0]   DA,
-  input  logic [68:0]   DB,
+  input  logic [67:0]   DB,
-  input  logic [68:0]   BWEBA, 
+  input  logic [67:0]   BWEBA, 
-  input  logic [68:0]   BWEBB, 
+  input  logic [67:0]   BWEBB, 
-  output logic [68:0]   QA,
+  output logic [67:0]   QA,
-  output logic [68:0]   QB
+  output logic [67:0]   QB
 );
 
    // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
-   generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+   generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
 			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
 
 endmodule

pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv

@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// ram2p1rwbe_64x32.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1r1wbe_64x32( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [5:0]    AA, 
+  input  logic [5:0]    AB, 
+  input  logic [31:0]   DA,
+  input  logic [31:0]   DB,
+  input  logic [31:0]   BWEBA, 
+  input  logic [31:0]   BWEBB, 
+  output logic [31:0]   QA,
+  output logic [31:0]   QB
+);
+
+   // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
+   generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule

pipelined/src/generic/mem/rom1p1r.sv

@@ -27,23 +27,21 @@
 
 `include "wally-config.vh"
 
-module rom1p1r
+module rom1p1r #(parameter ADDR_WIDTH = 8,
-  #(
+		 parameter DATA_WIDTH = 32, 
-	//--------------------------------------------------------------------------
+		 parameter PRELOAD_ENABLED = 0)
-	parameter ADDR_WIDTH = 8,
+  (input  logic                  clk,
-	// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
-	parameter DATA_WIDTH = 32, // Data Width in bits
-    parameter PRELOAD_ENABLED = 0
-	//----------------------------------------------------------------------
-	) (
-	   input logic 					 clk,
    input  logic                  ce,
    input  logic [ADDR_WIDTH-1:0] addr,
    output logic [DATA_WIDTH-1:0] dout
-	   );
+);
+
    // Core Memory
    logic [DATA_WIDTH-1:0] 	 ROM [(2**ADDR_WIDTH)-1:0];
+   if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
+      rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
+   end else begin
       always @ (posedge clk) begin
 	 if(ce) dout <= ROM[addr];    
       end
@@ -95,6 +93,7 @@ module rom1p1r
 	 ROM[41] = 64'h40a7853b4015551b;   
 	 ROM[42] = 64'h808210a7a02367c9;
       end 
-end
+    end 
+  end 
 
-endmodule // bytewrite_tdp_ram_rf
+endmodule 

pipelined/src/generic/mem/rom1p1r_128x32.sv

@@ -4,7 +4,7 @@
 // Written: james.stine@okstate.edu 28 January 2023
 // Modified: 
 //
-// Purpose: RAM wrapper for instantiating RAM IP
+// Purpose: ROM wrapper for instantiating ROM IP
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 

pipelined/src/generic/mem/rom1p1r_128x64.sv

@@ -0,0 +1,37 @@
+///////////////////////////////////////////
+// rom1p1r_128x64.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: ROM wrapper for instantiating ROM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module rom1p1r_128x64( 
+  input  logic 	      CLK, 
+  input  logic 	      CEB, 
+  input  logic [6:0]  A, 
+  output logic [63:0] Q
+);
+
+   // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
+   generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
+
+endmodule