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Give some cache mem inputs a better name

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This commit is contained in:
Jarred Allen 2021-03-24 12:31:01 -04:00
parent a51257abca
commit c1fe16b70b
1 changed files with 7 additions and 5 deletions
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12
wally-pipelined/src/cache/dmapped.sv vendored
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@ -5,6 +5,7 @@
// Modified: // Modified:
// //
// Purpose: An implementation of a direct-mapped cache memory // Purpose: An implementation of a direct-mapped cache memory
// This cache is read-only, so "write"s to the memory are loading new data
// //
// A component of the Wally configurable RISC-V project. // A component of the Wally configurable RISC-V project.
// //
@ -25,15 +26,15 @@
`include "wally-config.vh" `include "wally-config.vh"
module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, parameter WORDSIZE = `XLEN) ( module rodirectmappedmem #(parameter LINESIZE = 256, parameter NUMLINES = 512, parameter WORDSIZE = `XLEN) (
// Pipeline stuff // Pipeline stuff
input logic clk, input logic clk,
input logic reset, input logic reset,
// If flush is high, invalidate the entire cache // If flush is high, invalidate the entire cache
input logic flush, input logic flush,
// Select which address to read (broken for efficiency's sake) // Select which address to read (broken for efficiency's sake)
input logic [`XLEN-1:12] UpperPAdr, input logic [`XLEN-1:12] ReadUpperPAdr,
input logic [11:0] LowerAdr, input logic [11:0] ReadLowerAdr,
// Write new data to the cache // Write new data to the cache
input logic WriteEnable, input logic WriteEnable,
input logic [LINESIZE-1:0] WriteLine, input logic [LINESIZE-1:0] WriteLine,
@ -58,8 +59,8 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
// Swizzle bits to get the offset, set, and tag out of the read and write addresses // Swizzle bits to get the offset, set, and tag out of the read and write addresses
always_comb begin always_comb begin
// Read address // Read address
assign WordSelect = LowerAdr[OFFSETWIDTH-1:0]; assign WordSelect = ReadLowerAdr[OFFSETWIDTH-1:0];
assign ReadPAdr = {UpperPAdr, LowerAdr}; assign ReadPAdr = {ReadUpperPAdr, ReadLowerAdr};
assign ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; assign ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH];
assign ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; assign ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH];
// Write address // Write address
@ -89,3 +90,4 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
end end
endmodule endmodule