From c1fd7a95895708be60a921b2c828e500753f03e9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 18 Jun 2024 07:28:52 -0700 Subject: [PATCH] Removed unused signals --- src/cache/cache.sv | 2 +- src/cache/cacheLRU.sv | 3 +-- src/cache/cacheway.sv | 1 - src/fpu/fdivsqrt/fdivsqrt.sv | 4 +--- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 5 ++-- src/fpu/fpu.sv | 2 +- src/fpu/fround.sv | 3 +-- src/fpu/postproc/shiftcorrection.sv | 1 - src/fpu/unpack.sv | 14 +++++------ src/fpu/unpackinput.sv | 4 ++-- src/ieu/bmu/bmuctrl.sv | 1 - src/ieu/controller.sv | 3 +-- src/ifu/bpred/bpred.sv | 37 ++++++++++++----------------- src/ifu/bpred/btb.sv | 13 +++++----- src/ifu/bpred/gshare.sv | 2 +- src/mmu/hptw.sv | 10 ++++---- src/mmu/tlb/tlb.sv | 2 +- src/mmu/tlb/tlblru.sv | 1 - src/mmu/tlb/vm64check.sv | 8 +++---- src/uncore/uartPC16550D.sv | 10 +++----- 20 files changed, 51 insertions(+), 75 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 3569a92e3..11f03d8ef 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -128,7 +128,7 @@ module cache import cvw::*; #(parameter cvw_t P, if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag, .LRUWriteEn, - .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); + .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else assign VictimWay = 1'b1; // one hot. diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 8b88e0343..79b277a03 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -40,7 +40,6 @@ module cacheLRU input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set - input logic ClearValid, // Clear the dirty bit in the selected way and set input logic InvalidateCache, // Clear all valid bits output logic [NUMWAYS-1:0] VictimWay // LRU selects a victim to evict ); @@ -145,7 +144,7 @@ module cacheLRU // LRU read path with write forwarding assign ReadLRU = LRUMemory[CacheSetTag]; assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag); - mux2 #(NUMWAYS-1) ReadLRUmux(LRUMemory[CacheSetTag], NextLRU, ForwardLRU, BypassedLRU); + mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU); flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU); endmodule diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 7406ebd83..fb9d39f41 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -76,7 +76,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic ClearValidWay; logic SetDirtyWay; logic ClearDirtyWay; - logic SelNonHit; logic SelectedWay; logic InvalidateCacheDelay; diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 578996315..0511e283c 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -69,7 +69,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Integer div/rem signals logic BZeroM; // Denominator is zero - logic IntDivM; // Integer operation logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor @@ -80,8 +79,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( .FmtE, .Bias(BiasE), .Nf(NfE), .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE, // Int-specific .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE, - .BZeroM, .IntNormShiftM, .AM, - .IntDivM, .W64M, .ALTBM, .AsM, .BsM); + .BZeroM, .IntNormShiftM, .AM, .W64M, .ALTBM, .AsM, .BsM); fdivsqrtfsm #(P) fdivsqrtfsm( // FSM .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index afdb5cb92..5e305240f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -47,7 +47,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( output logic ISpecialCaseE, output logic [P.DURLEN-1:0] CyclesE, output logic [P.DIVBLEN-1:0] IntNormShiftM, - output logic ALTBM, IntDivM, W64M, + output logic ALTBM, W64M, output logic AsM, BsM, BZeroM, output logic [P.XLEN-1:0] AM ); @@ -229,7 +229,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( mux2 #(P.DIVBLEN) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE); // pipeline registers - flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM); @@ -239,7 +238,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( if (P.XLEN==64) flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); end else - assign {ALTBM, IntDivM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0; + assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0; endmodule diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 122888509..7619b92af 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -279,7 +279,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( logic [P.FLEN-1:0] FliResE; // Zfa Floating-point load immediate value // fround - fround #(P) fround(.X(XE), .Xs(XsE), .Xe(XeE), .Xm(XmE), + fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE), .XNaN(XNaNE), .XSNaN(XSNaNE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE), .ZfaFRoundNX(ZfaFRoundNXE), .FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE)); diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index bf4a4f7ad..3265ec626 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -28,7 +28,6 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fround import cvw::*; #(parameter cvw_t P) ( - input logic [P.FLEN-1:0] X, // input before unpacking input logic Xs, // input's sign input logic [P.NE-1:0] Xe, // input's exponent input logic [P.NF:0] Xm, // input's fraction with leading integer bit (U1.NF) @@ -45,7 +44,7 @@ module fround import cvw::*; #(parameter cvw_t P) ( logic [P.NE-1:0] E, Xep1; logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd; - logic [P.FLEN-1:0] W, PackedW; + logic [P.FLEN-1:0] W; logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf; // Unbiased exponent diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index 03ec66a72..0524ca364 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -45,7 +45,6 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( output logic [P.NE+1:0] Ue // corrected exponent for divider ); - logic [P.NORMSHIFTSZ-1:0] CorrShifted; // the shifted sum after LZA correction logic ResSubnorm; // is the result Subnormal logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction logic LeftShiftQm; // should the divsqrt result be shifted one to the left diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index b24554fc0..e0e35312f 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -46,23 +46,21 @@ module unpack import cvw::*; #(parameter cvw_t P) ( output logic [P.LOGFLEN-1:0] Nf // Number of fractional bits ); - logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero - logic XFracZero, YFracZero, ZFracZero; // is the fraction zero logic YExpMax, ZExpMax; // is the exponent all 1s unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive, - .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), + .NaN(XNaN), .SNaN(XSNaN), + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .Subnorm(XSubnorm), .PostBox(XPostBox)); unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive, - .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), + .NaN(YNaN), .SNaN(YSNaN), + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .Subnorm(), .PostBox()); unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive, - .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), + .NaN(ZNaN), .SNaN(ZSNaN), + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .Subnorm(), .PostBox()); // look up bias and fractional bits for the given format diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 1b27c439b..c90ede41d 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -39,8 +39,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( output logic SNaN, // is the number a signaling NaN output logic Zero, // is the number zero output logic Inf, // is the number infinity - output logic ExpNonZero, // is the exponent not zero - output logic FracZero, // is the fraction zero output logic ExpMax, // does In have the maximum exponent (NaN or Inf) output logic Subnorm, // is the number subnormal output logic [P.FLEN-1:0] PostBox // Number reboxed correctly as a NaN @@ -48,6 +46,8 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( logic [P.NF-1:0] Frac; // Fraction of XYZ logic BadNaNBox; // incorrectly NaN Boxed + logic FracZero; // is the fraction zero + logic ExpNonZero; // is the exponent non-zero logic [P.FLEN-1:0] In; // Gate input when FPU is not active to save power and simulation diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 834270685..2827ac735 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -31,7 +31,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Decode stage control signals - input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage input logic ALUOpD, // Regular ALU Operation output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 21f024942..ce37cd051 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -158,7 +158,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [3:0] CMOpD, CMOpE; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero logic IFUPrefetchD; // instruction prefetch logic LSUPrefetchD, LSUPrefetchE; // data prefetch - logic CMOStallD; // Structural hazards from cache management ops logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check) @@ -329,7 +328,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic BSubArithD; // TRUE for BMU ext, clr, andn, orn, xnor logic BALUSrcBD; // BMU alu src select signal - bmuctrl #(P) bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, + bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE); if (P.ZBA_SUPPORTED) begin diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 6080cacb5..f64144d87 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -72,33 +72,26 @@ module bpred import cvw::*; #(parameter cvw_t P) ( logic [1:0] BPDirPredF; - logic [P.XLEN-1:0] BPBTAF, RASPCF; - logic BPPCWrongE; - logic IClassWrongE; + logic [P.XLEN-1:0] BPBTAF, RASPCF; logic BPDirPredWrongE; logic BPPCSrcF; - logic [P.XLEN-1:0] BPPCF; - logic [P.XLEN-1:0] PC0NextF; - logic [P.XLEN-1:0] PCCorrectE; - logic [3:0] WrongPredInstrClassD; + logic [P.XLEN-1:0] BPPCF; + logic [P.XLEN-1:0] PC0NextF; + logic [P.XLEN-1:0] PCCorrectE; - logic BTBTargetWrongE; logic RASTargetWrongE; - logic [P.XLEN-1:0] BPBTAD; - - logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; - logic BPBranchF, BPJumpF, BPReturnF, BPCallF; - logic BPBranchD, BPJumpD, BPReturnD, BPCallD; - logic ReturnD, CallD; - logic ReturnE, CallE; - logic BranchM, JumpM, ReturnM, CallM; - logic BranchW, JumpW, ReturnW, CallW; - logic BPReturnWrongD; - logic [P.XLEN-1:0] BPBTAE; - logic BPBTAWrongM; - logic PCSrcM; + logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; + logic BPBranchF, BPJumpF, BPReturnF, BPCallF; + logic BPBranchD, BPJumpD, BPReturnD, BPCallD; + logic ReturnD, CallD; + logic ReturnE, CallE; + logic BranchM, JumpM, ReturnM, CallM; + logic BranchW, JumpW, ReturnW, CallW; + logic BPReturnWrongD; + logic BPBTAWrongM; + logic PCSrcM; // Part 1 branch direction prediction if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor @@ -154,7 +147,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( btb #(P, P.BTB_SIZE) TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, - .BPBTAF, .BPBTAD, .BPBTAE, + .BPBTAF, .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), .BPBTAWrongM, .IClassWrongM, diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 1ac95bed9..acd61df67 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -36,8 +36,6 @@ module btb import cvw::*; #(parameter cvw_t P, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, input logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages output logic [P.XLEN-1:0] BPBTAF, // BTB's guess at PC - output logic [P.XLEN-1:0] BPBTAD, - output logic [P.XLEN-1:0] BPBTAE, output logic [3:0] BTBIClassF, // BTB's guess at instruction class output logic BPBTAWrongM, // update @@ -52,11 +50,12 @@ module btb import cvw::*; #(parameter cvw_t P, logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex; logic MatchD, MatchE, MatchM, MatchW, MatchX; - logic [P.XLEN+3:0] ForwardBTBPredF; - logic [P.XLEN+3:0] TableBTBPredF; - logic [P.XLEN-1:0] IEUAdrW; - logic [P.XLEN-1:0] PCW; - logic BTBWrongE, BPBTAWrongE; + logic [P.XLEN+3:0] ForwardBTBPredF; + logic [P.XLEN+3:0] TableBTBPredF; + logic [P.XLEN-1:0] IEUAdrW; + logic [P.XLEN-1:0] PCW; + logic [P.XLEN-1:0] BPBTAD, BPBTAE; + logic BPBTAWrongE; logic BTBWrongM; diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 9192a7cf5..4cf15044a 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -44,7 +44,7 @@ module gshare import cvw::*; #(parameter cvw_t P, input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM, MatchW; + logic MatchD, MatchE, MatchM, MatchW; logic MatchX; logic [1:0] PHTBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index b86ee6a95..5952266e5 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -49,7 +49,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( input logic ITLBMissF, input logic DTLBMissM, input logic FlushW, - input logic InstrUpdateDAF, + input logic InstrUpdateDAF, // *** unused; RT, can we delete or is this a bug? input logic DataUpdateDAM, output logic [P.XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs @@ -105,7 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault; logic HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay; logic HPTWAccessFaultDelay; - logic TakeHPTWFault, TakeHPTWFaultDelay; + logic TakeHPTWFault; logic [P.XLEN-1:0] ReadDataNoXM; logic PBMTFaultM; logic HPTWFaultM; @@ -120,9 +120,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; - flopr #(7) HPTWAccesFaultReg(clk, reset, {TakeHPTWFault, HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, + flopr #(6) HPTWAccesFaultReg(clk, reset, {HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault}, - {TakeHPTWFaultDelay, HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay, + {HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay, HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay}); assign TakeHPTWFault = WalkerState != IDLE; @@ -320,7 +320,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay. // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. - assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; + assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; // *** unused - RT, can we delete? assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 2246dcbc4..95a1432b4 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -115,7 +115,7 @@ module tlb import cvw::*; #(parameter cvw_t P, .TLBMiss, .TLBHit, .TLBPageFault, .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType); - tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .TLBHit, .WriteEnables); + tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .Matches, .TLBHit, .WriteEnables); tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS) tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs, .SATP_ASID, .Matches, .HitPageType, .CAMHit); diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 96359590b..6700ddcd0 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -31,7 +31,6 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( input logic clk, reset, input logic TLBWrite, - input logic TLBFlush, input logic [TLB_ENTRIES-1:0] Matches, input logic TLBHit, output logic [TLB_ENTRIES-1:0] WriteEnables diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index 229bb5a5f..6f2d3c2d4 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -28,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module vm64check import cvw::*; #(parameter cvw_t P) ( - input logic [P.SVMODE_BITS-1:0] SATP_MODE, - input logic [P.XLEN-1:0] VAdr, - output logic SV39Mode, - output logic UpperBitsUnequal + input logic [P.SVMODE_BITS-1:0] SATP_MODE, + input logic [P.XLEN-1:0] VAdr, + output logic SV39Mode, + output logic UpperBitsUnequal ); if (P.XLEN == 64) begin diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index c4c1dc27f..7b27ef8e7 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -94,7 +94,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( logic [7:0] txfifo[15:0]; logic [4:0] rxfifotailunwrapped; logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; - logic [3:0] rxfifoentries, txfifoentries; + logic [3:0] rxfifoentries; logic [3:0] rxbitsexpected, txbitsexpected; // receive data @@ -484,12 +484,8 @@ module uartPC16550D #(parameter UART_PRESCALE) ( HeadPointerLastMove <= 1'b0; end - assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove; - // verilator lint_off WIDTH - assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : - (txfifohead + 16 - txfifotail); - // verilator lint_on WIDTH - assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove; + assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove; + assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove; // transmit buffer ready bit always_ff @(posedge PCLK) // track txrdy for DMA mode (FCR3 = FCR0 = 1)