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Fixed debug signal names. Builds on the fpga. Bug in the crossbar.

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This commit is contained in:
Jacob Pease 2023-02-16 17:33:21 -06:00
parent a07d61ec43
commit c1e7526570
3 changed files with 2 additions and 3 deletions
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2
bin/wally-tool-chain-install.sh
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@ -31,7 +31,7 @@ export PATH=$PATH:$RISCV/bin
set -e # break on error set -e # break on error
NUM_THREADS=1 # for low memory machines > 16GiB NUM_THREADS=32 # for low memory machines > 16GiB
#NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=8 # for >= 32GiB
#NUM_THREADS=16 # for >= 64GiB #NUM_THREADS=16 # for >= 64GiB

2
fpga/constraints/debug2.xdc
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@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property port_width 1 [get_debug_ports u_ila_0/probe54]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]] connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/StallFCause ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe55] set_property port_width 1 [get_debug_ports u_ila_0/probe55]

1
fpga/constraints/marked_debug.txt
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@ -14,7 +14,6 @@ ieu/regfile.sv: logic rf
ieu/datapath.sv: logic RegWriteW ieu/datapath.sv: logic RegWriteW
hazard/hazard.sv: logic BPPredWrongE hazard/hazard.sv: logic BPPredWrongE
hazard/hazard.sv: logic LoadStallD hazard/hazard.sv: logic LoadStallD
hazard/hazard.sv: logic LSUStallM
hazard/hazard.sv: logic FCvtIntStallD hazard/hazard.sv: logic FCvtIntStallD
hazard/hazard.sv: logic DivBusyE hazard/hazard.sv: logic DivBusyE
hazard/hazard.sv: logic EcallFaultM hazard/hazard.sv: logic EcallFaultM