diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 49413e300..6f09c4f95 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -203,13 +203,13 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit @@ -220,7 +220,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr @@ -328,9 +328,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode @@ -371,19 +376,16 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress @@ -462,29 +464,8 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM -add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE -add wave -noupdate /testbench/dut/hart/ifu/PCSrcE -add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE -add wave -noupdate /testbench/dut/hart/ieu/c/BranchE -add wave -noupdate /testbench/dut/hart/ifu/PCLinkE -add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM -add wave -noupdate /testbench/dut/hart/ifu/PCF -add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR -add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM -add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB -add wave -noupdate /testbench/dut/hart/ifu/temp -add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM -add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM -add wave -noupdate /testbench/dut/hart/lsu/BusCurrState -add wave -noupdate /testbench/dut/hart/lsu/BasePAdrM -add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBPAdrM -add wave -noupdate /testbench/dut/hart/lsu/FetchCountFlag -add wave -noupdate /testbench/dut/hart/lsu/FetchCount -add wave -noupdate /testbench/dut/hart/lsu/DCfromAHBAck -add wave -noupdate /testbench/dut/hart/lsu/BUSACK -add wave -noupdate /testbench/dut/hart/lsu/DCFetchLine TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {2947 ns} 0} +WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {207375 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -500,4 +481,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2791 ns} {3081 ns} +WaveRestoreZoom {207017 ns} {208185 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index bff68e451..0cd5d394b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -131,7 +131,7 @@ module dcache mux4 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(0), // *** REMOVE + .d1(7'b0), // *** REMOVE .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d3(FlushAdr), .s(SelAdrM), diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 23ff5d17d..c098a8c26 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -94,9 +94,7 @@ module lsu logic [`XLEN+1:0] IEUAdrExtM; logic DTLBMissM; logic DTLBWriteM; - logic HPTWStall; - logic [`PA_BITS-1:0] HPTWAdr; - logic HPTWRead; + logic [1:0] DCRWM; logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; @@ -110,151 +108,191 @@ module lsu logic CacheableM; logic SelHPTW; - logic [2:0] HPTWSize; logic DCCommittedM; logic CommittedMfromBus; - logic AnyCPUReqM; - logic MemAfterIWalkDone; logic BusStall; - typedef enum {STATE_T0_READY, - STATE_T0_REPLAY, - STATE_T3_DTLB_MISS, - STATE_T4_ITLB_MISS, - STATE_T5_ITLB_MISS, - STATE_T7_DITLB_MISS} statetype; - - statetype InterlockCurrState, InterlockNextState; logic InterlockStall; - logic SelReplayCPURequest; logic IgnoreRequest; - - assign AnyCPUReqM = (|MemRWM) | (|AtomicM); - - always_ff @(posedge clk) - if (reset) InterlockCurrState <= #1 STATE_T0_READY; - else InterlockCurrState <= #1 InterlockNextState; - - always_comb begin - case(InterlockCurrState) - STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; - else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; - else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; - else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; - else InterlockNextState = STATE_T0_READY; - STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T3_DTLB_MISS; - STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; - else InterlockNextState = STATE_T4_ITLB_MISS; - STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T5_ITLB_MISS; - STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; - else InterlockNextState = STATE_T7_DITLB_MISS; - default: InterlockNextState = STATE_T0_READY; - endcase - end // always_comb - - // signal to CPU it needs to wait on HPTW. - /* -----\/----- EXCLUDED -----\/----- - // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates - // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. - assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | - (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); - - -----/\----- EXCLUDED -----/\----- */ - - always_comb begin - InterlockStall = 1'b0; - case(InterlockCurrState) - STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; - STATE_T3_DTLB_MISS: InterlockStall = 1'b1; - STATE_T4_ITLB_MISS: InterlockStall = 1'b1; - STATE_T5_ITLB_MISS: InterlockStall = 1'b1; - STATE_T7_DITLB_MISS: InterlockStall = 1'b1; - default: InterlockStall = 1'b0; - endcase - end - - - // When replaying CPU memory request after PTW select the IEUAdrM for correct address. - assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); - assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | - (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); - assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | - ((InterlockCurrState == STATE_T0_REPLAY) - & (ExceptionM | PendingInterruptM)); - - - flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); + assign IEUAdrExtM = {2'b00, IEUAdrM}; - // *** add generate to conditionally create hptw, lsuArb, and mmu - // based on `MEM_VIRTMEM - hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, - .ITLBMissF(ITLBMissF & ~PendingInterruptM), - .DTLBMissM(DTLBMissM & ~PendingInterruptM), - .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, - .HPTWReadPTE(ReadDataM), - .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); + generate + if(`MEM_VIRTMEM) begin : MEM_VIRTMEM + logic AnyCPUReqM; + logic [`PA_BITS-1:0] HPTWAdr; + logic HPTWRead; + logic [2:0] HPTWSize; + logic SelReplayCPURequest; + + typedef enum {STATE_T0_READY, + STATE_T0_REPLAY, + STATE_T3_DTLB_MISS, + STATE_T4_ITLB_MISS, + STATE_T5_ITLB_MISS, + STATE_T7_DITLB_MISS} statetype; + + statetype InterlockCurrState, InterlockNextState; + + assign AnyCPUReqM = (|MemRWM) | (|AtomicM); + + always_ff @(posedge clk) + if (reset) InterlockCurrState <= #1 STATE_T0_READY; + else InterlockCurrState <= #1 InterlockNextState; + + always_comb begin + case(InterlockCurrState) + STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; + else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; + else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; + else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; + else InterlockNextState = STATE_T0_READY; + STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T0_READY; + STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T3_DTLB_MISS; + STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; + else InterlockNextState = STATE_T4_ITLB_MISS; + STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T5_ITLB_MISS; + STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; + else InterlockNextState = STATE_T7_DITLB_MISS; + default: InterlockNextState = STATE_T0_READY; + endcase + end // always_comb + + // signal to CPU it needs to wait on HPTW. + /* -----\/----- EXCLUDED -----\/----- + // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates + // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. + assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | + (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); + + -----/\----- EXCLUDED -----/\----- */ + + always_comb begin + InterlockStall = 1'b0; + case(InterlockCurrState) + STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; + STATE_T3_DTLB_MISS: InterlockStall = 1'b1; + STATE_T4_ITLB_MISS: InterlockStall = 1'b1; + STATE_T5_ITLB_MISS: InterlockStall = 1'b1; + STATE_T7_DITLB_MISS: InterlockStall = 1'b1; + default: InterlockStall = 1'b0; + endcase + end + + // When replaying CPU memory request after PTW select the IEUAdrM for correct address. + assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); + assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); + assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | + ((InterlockCurrState == STATE_T0_REPLAY) + & (ExceptionM | PendingInterruptM)); + + + // *** add generate to conditionally create hptw, lsuArb, and mmu + // based on `MEM_VIRTMEM + hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, + .ITLBMissF(ITLBMissF & ~PendingInterruptM), + .DTLBMissM(DTLBMissM & ~PendingInterruptM), + .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, + .HPTWReadPTE(ReadDataM), + .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); + + // arbiter between IEU and hptw + + // multiplex the outputs to LSU + mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); + mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); + mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); + mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); + mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); + + assign CPUBusy = StallW & ~SelHPTW; + // always block interrupts when using the hardware page table walker. + assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; + + // this is for the d cache SRAM. + // turns out because we cannot pipeline hptw requests we don't need this register + //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle + + //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; + //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; + //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; + //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; + + + // Specify which type of page fault is occurring + // *** `MEM_VIRTMEM + assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; + + assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; + + end // if (`MEM_VIRTMEM) + else begin + assign InterlockStall = 1'b0; + + assign DCAdrE = LsuAdrE; + assign SelHPTW = 1'b0; + assign IgnoreRequest = 1'b0; + + assign PTE = '0; + assign PageType = '0; + assign DTLBWriteM = 1'b0; + assign ITLBWriteF = 1'b0; + + assign LsuRWM = MemRWM; + assign LsuFunct3M = Funct3M; + assign LsuAtomicM = AtomicM; + assign LsuAdrE = IEUAdrE[11:0]; + assign LsuPAdrM = IEUAdrExtM; + assign CPUBusy = StallW; + assign CommittedM = CommittedMfromBus; + + assign DTLBLoadPageFaultM = 1'b0; + assign DTLBStorePageFaultM = 1'b0; + end + endgenerate + + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) + dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .PrivilegeModeW, .DisableTranslation(SelHPTW), + .PAdr(LsuPAdrM), + .VAdr(IEUAdrM), + .Size(LsuFunct3M[1:0]), + .PTE, + .PageTypeWriteVal(PageType), + .TLBWrite(DTLBWriteM), + .TLBFlush(DTLBFlushM), + .PhysicalAddress(MemPAdrM), + .TLBMiss(DTLBMissM), + .Cacheable(CacheableM), + .Idempotent(), .AtomicAllowed(), + .TLBPageFault(DTLBPageFaultM), + .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, + .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), + .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW + ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? assign LSUStall = DCacheStall | InterlockStall | BusStall; - // arbiter between IEU and hptw - - // multiplex the outputs to LSU - mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); - mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); - mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); - mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); - assign IEUAdrExtM = {2'b00, IEUAdrM}; - mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); - - assign CPUBusy = StallW & ~SelHPTW; - // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; - - // this is for the d cache SRAM. - // turns out because we cannot pipeline hptw requests we don't need this register - //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle - - //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; - //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; - //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; - //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; - - mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(SelHPTW), - .PAdr(LsuPAdrM), - .VAdr(IEUAdrM), - .Size(LsuFunct3M[1:0]), - .PTE, - .PageTypeWriteVal(PageType), - .TLBWrite(DTLBWriteM), - .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), - .TLBMiss(DTLBMissM), - .Cacheable(CacheableM), - .Idempotent(), .AtomicAllowed(), - .TLBPageFault(DTLBPageFaultM), - .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, - .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), - .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW - ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? + // If the CPU's (not HPTW's) request is a page fault. + assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; + assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; // Move generate from lrsc to outside this module. @@ -269,10 +307,6 @@ module lsu end endgenerate - // Specify which type of page fault is occurring - // *** `MEM_VIRTMEM - assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; // Determine if an Unaligned access is taking place // hptw guarantees alignment, only check inputs from IEU. @@ -284,15 +318,11 @@ module lsu 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd endcase - // If the CPU's (not HPTW's) request is a page fault. - assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; - assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; // conditional // 1. ram // controlled by `MEM_DTIM // 2. cache `MEM_DCACHE // 3. wire pass-through - assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE[11:0]; localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE);