From c15517d334c247e45a84fbe8a79beacc7b8501c8 Mon Sep 17 00:00:00 2001
From: Shreya Sanghai <ssanghai@hmc.edu>
Date: Mon, 7 Mar 2022 17:36:05 +0000
Subject: [PATCH] removed reminant changes

---
 synthDC/scripts/synth.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 04366ed6c..3146e14ed 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -22,7 +22,7 @@ set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 
-# eval file copy -force ${cfg} {hdl/}
+eval file copy -force ${cfg} {hdl/}
 eval file copy -force ${cfg} $outputDir
 eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
@@ -34,7 +34,7 @@ if { $saifpower == 1 } {
 }
 
 # Verilog files
-set my_verilog_files [glob hdl/* outputDir/wally-config.vh]
+set my_verilog_files [glob hdl/*]
 
 # Set toplevel
 set my_toplevel $::env(DESIGN)