diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 8a0cdceca..59ae6e707 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b
+Subproject commit 59ae6e7073ff40c7e1a1556547b2e8b2ba03ea04
diff --git a/addins/riscv-dv b/addins/riscv-dv
index a7e27bc04..f0c570d11 160000
--- a/addins/riscv-dv
+++ b/addins/riscv-dv
@@ -1 +1 @@
-Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
+Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
diff --git a/bin/regression-wally b/bin/regression-wally
index a73f937a5..67aca568b 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -12,7 +12,6 @@
 ##################################
 import sys,os,shutil
 import multiprocessing
-#import os
 from collections import namedtuple
 from multiprocessing import Pool, TimeoutError
 
@@ -24,7 +23,6 @@ from multiprocessing import Pool, TimeoutError
 # The element consists of the configuration name, a list of test suites to run, 
 # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
 
-INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
 tests = [
         ["rv32e", ["arch32e"]],
         ["rv32i", ["arch32i"]],
@@ -34,10 +32,22 @@ tests = [
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", 
                     "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", 
                     "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
-        ["rv64i", ["arch64i"]],
-        ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
+        ["rv64i", ["arch64i"]]
         ]
 
+
+# Separate test for full buildroot run
+tests_buildrootshort = [
+                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output  
+                        "OpenSBI v", "buildroot_uart.out"]
+    ]
+
+tests_buildrootboot = [
+                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], 
+                        "WallyHostname login: ", "buildroot_uart.out"]
+    ]
+
+
 # Separate out floating-point tests for RV64 to speed up coverage
 tests64gc_nofp = [
         ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",
@@ -176,7 +186,7 @@ bpredtests = [
 # Data Types & Functions
 ##################################
 
-TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
+TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
 # name:     the name of this test configuration (used in printing human-readable
 #           output and picking logfile names)
 # cmd:      the command to run to test (should include the logfile as '{}', and
@@ -184,6 +194,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
 # grepstr:  the string to grep through the log file for. The test succeeds iff
 #           grep finds that string in the logfile (is used by grep, so it may
 #           be any pattern grep accepts, see `man 1 grep` for more info).
+# grepfile:  a string containing the location of the file to be searched for output
 
 class bcolors:
     HEADER = '\033[95m'
@@ -197,6 +208,7 @@ class bcolors:
     UNDERLINE = '\033[4m'
 
 def addTests(tests, sim):
+    sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
     for test in tests:
         config = test[0];
         suites = test[1];
@@ -210,36 +222,38 @@ def addTests(tests, sim):
             gs = "All tests ran without failures"
         cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
         for t in suites:
+            sim_log = sim_logdir + config + "_" + t + ".log"
+            if (len(test) >= 5):
+                grepfile = sim_logdir + test[4]
+            else:
+                grepfile = sim_log
             tc = TestCase(
                     name=t,
                     variant=config,
-                    cmd=cmdPrefix + " " + t + args,
-                    grepstr=gs)
+                    cmd=cmdPrefix + " " + t + args + " > " + sim_log,
+                    grepstr=gs,
+                    grepfile = grepfile)
             configs.append(tc)
 
-def search_log_for_text(text, logfile):
+def search_log_for_text(text, grepfile):
     """Search through the given log file for text, returning True if it is found or False if it is not"""
-    grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
+    grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
 #    print("  search_log_for_text invoking %s" % grepcmd)
     return os.system(grepcmd) == 0
 
 def run_test_case(config):
     """Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
-    logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log"   ### *** fix hardwiring to questa log
-    #cmd = config.cmd + " > " + logname
-    if ("lint-wally" in config.cmd):
-        cmd = config.cmd + " | tee " + logname
-    else:
-        cmd = config.cmd + " > " + logname
+    grepfile = config.grepfile
+    cmd = config.cmd
     os.chdir(regressionDir)
-#    print("  run_test_case invoking %s" % cmd)
+    # print("  run_test_case invoking %s" % cmd)
     os.system(cmd)
-    if search_log_for_text(config.grepstr, logname):
+    if search_log_for_text(config.grepstr, grepfile):
         print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
         return 0
     else:
         print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
-        print("  Check %s" % logname)
+        print("  Check %s" % grepfile)
         return 1
 
 ##################################
@@ -258,12 +272,13 @@ coverage = '--coverage' in sys.argv
 fp = '--fp' in sys.argv
 nightly = '--nightly' in sys.argv
 testfloat = '--testfloat' in sys.argv
+buildroot = '--buildroot' in sys.argv
 
 if (nightly):
     nightMode = "--nightly";
     sims = ["questa", "verilator", "vcs"]
 else:
-    nightMode = "";
+    nightMode = ""
     sims = [defaultsim]
 
 if (coverage):  # only run RV64GC tests in coverage mode
@@ -277,9 +292,9 @@ configs = [
     TestCase(
         name="lints",
         variant="all",
-        cmd="lint-wally " + nightMode,
-        grepstr="lints run with no errors or warnings"
-    )
+        cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
+        grepstr="lints run with no errors or warnings",
+        grepfile = WALLY + "/sim/questa/logs/all_lints.log")
     ]
 
 if (coverage):  # only run RV64GC tests on Questa in coverage mode
@@ -291,9 +306,13 @@ else:
         addTests(tests, sim)
         addTests(tests64gc_nofp, sim)
         addTests(tests64gc_fp, sim)
+
     # run derivative configurations in nightly regression
-    if (nightly):
-        addTests(derivconfigtests, defaultsim)
+if (nightly):
+    addTests(derivconfigtests, defaultsim)
+    addTests(tests_buildrootboot, defaultsim)
+else:
+    addTests(tests_buildrootshort, defaultsim)
 
 # testfloat tests
 if (testfloat):
@@ -305,11 +324,13 @@ if (testfloat):
         if ("f_" in config):
             tests.remove("cvtfp")
         for test in tests:
+            sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" # TODO: Change hardcoded questa log directory to simulator
             tc = TestCase(
                     name=test,
                     variant=config,
-                    cmd="wsim --tb testbench_fp " + config + " " + test,
-                    grepstr="All Tests completed with          0 errors")
+                    cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
+                    grepstr="All Tests completed with          0 errors",
+                    grepfile = sim_log)
             configs.append(tc)
 
 
@@ -348,11 +369,13 @@ if (testfloat):
         if ("f_" in config):
             tests.remove("cvtfp")
         for test in tests:
+            sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log"
             tc = TestCase(
                     name=test,
                     variant=config,
-                    cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
-                    grepstr="All Tests completed with          0 errors")
+                    cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log,
+                    grepstr="All Tests completed with          0 errors",
+                    grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
             configs.append(tc)
 
 
@@ -370,26 +393,17 @@ def main():
         os.chdir(regressionDir)
         os.system('./make-tests.sh | tee ./logs/make-tests.log')
 
-    if '--all' in sys.argv:
-        TIMEOUT_DUR = 30*7200 # seconds
-        #configs.append(getBuildrootTC(boot=True))
-    elif '--buildroot' in sys.argv:
-        TIMEOUT_DUR = 30*7200 # seconds
-        #configs=[getBuildrootTC(boot=True)]
+    if '--buildroot' in sys.argv:
+        TIMEOUT_DUR = 60*7200 # 5 days to run
     elif '--coverage' in sys.argv:
-        TIMEOUT_DUR = 20*60 # seconds    
-    #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
-    #   Also it is slow to run.   
-    #    configs.append(getBuildrootTC(boot=False))
+        TIMEOUT_DUR = 20*60 # seconds
         os.system('rm -f questa/cov/*.ucdb')
     elif '--nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
-        #configs.append(getBuildrootTC(boot=False))
     elif '--testfloat' in sys.argv:
         TIMEOUT_DUR = 60*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
-        #configs.append(getBuildrootTC(boot=False))
 
     # Scale the number of concurrent processes to the number of test cases, but
     # max out at a limited number of concurrent processes to not overwhelm the system
diff --git a/docs/docker/Makefile b/docs/docker/Makefile
index 5493555c9..82560d8cb 100644
--- a/docs/docker/Makefile
+++ b/docs/docker/Makefile
@@ -3,16 +3,30 @@ CVW_GIT?=""
 
 commanline:
 	podman run -it --rm \
-    -v cvw_temp:/home/cad/cvw \
-    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    wallysoc/regression_wally /bin/bash
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	wallysoc/regression_wally /bin/bash
 
 regression_openhw_cvw:
 	podman run \
 	-e CVW_GIT=$(CVW_GIT) \
-    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
-    -v cvw_temp:/home/cad/cvw \
-    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    --rm wallysoc/regression_wally
\ No newline at end of file
+	-e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	--rm wallysoc/regression_wally
+
+push_hub:
+	podman push wallysoc/ubuntu_wally:latest
+	podman push wallysoc/toolchains_wally:latest
+	podman push wallysoc/regression_wally:latest
+
+update_ubuntu:
+	podman build -t wallysoc/ubuntu_wally -f Dockerfile.ubuntu .
+
+update_toolchains:
+	podman build -t wallysoc/toolchains_wally -f Dockerfile.builds .
+
+update_regression:
+	podman build -t wallysoc/regression_wally -f Dockerfile.regression .
\ No newline at end of file
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index e6807a6a6..df4ed0e2a 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -57,7 +57,8 @@ PreProcessFiles:
 	# modify config  *** RT: eventually setup for variably defined sized memory
 	#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
-	sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 
 $(dst)/%.log: %.tcl
 	mkdir -p IP
diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh
index b9f8c86f8..5f8e3fce1 100755
--- a/fpga/generator/insert_debug_comment.sh
+++ b/fpga/generator/insert_debug_comment.sh
@@ -4,7 +4,7 @@
 ##
 ## Written: Rose Thompson ross1728@gmail.com
 ## Created: 20 January 2023
-## Modified: 16 April 2024
+## Modified: 22 April 2024
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ## https://github.com/openhwgroup/cvw
@@ -29,21 +29,12 @@
 # Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
 copiedDir="../src/CopiedFiles_do_not_add_to_repo"
 while read line; do
-    # older versions of bash are incompatible with readarray -d :(
-    #readarray -d ":" -t StrArray <<< "$line"
-    #file="${copiedDir}/${StrArray[0]}"
-    #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
-    fileName=`echo $line | cut -d  ":" -f 1`
-    file=${copiedDir}/$fileName
-    signal=`echo $line | cut -d  ":" -f 2`
-    echo $file
-    echo $signal
+    readarray -d ":" -t StrArray <<< "$line"
+    file="${copiedDir}/${StrArray[0]}"
+    signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
     readarray -d " " -t SigArray <<< $signal
-    sigType=`echo $signal | cut -d " " -f 1`
-    sigType=`echo $sigType | awk '{$1=$1};1'`
-    sigName=`echo $signal | cut -d " " -f 2`
-    sigName=`echo $sigName | awk '{$1=$1};1'`
-    #sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
-    #sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
-    find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" 
+    sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
+    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"`
+    filepath=`find $copiedDir -wholename $file`
+    sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath
 done < ../constraints/marked_debug.txt
diff --git a/sim/questa/wave.do b/sim/questa/wave.do
index bb6b1d54b..9947bcd6f 100644
--- a/sim/questa/wave.do
+++ b/sim/questa/wave.do
@@ -471,88 +471,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/Dout
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
-add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
-add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/INTR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask
+add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME
+add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
index 542b09d1c..f4f8c846f 100644
--- a/sim/verilator/Makefile
+++ b/sim/verilator/Makefile
@@ -1,14 +1,28 @@
+SHELL := /bin/bash
 .PHONY: profile run questa clean
 
+# verilator configurations
 OPT=
 PARAMS?=-DVERILATOR=1 --no-trace-top
 NONPROF?=--stats
 VERILATOR_DIR=${WALLY}/sim/verilator
 SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
 
+
 WALLYCONF?=rv64gc
 TEST?=arch64i
 
+# constants
+# assume WALLY variable is correctly configured in the shell environment
+WORKING_DIR=${WALLY}/sim/verilator
+TARGET=$(WORKING_DIR)/target
+# INCLUDE_PATH are pathes that Verilator should search for files it needs
+INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
+# SOURCES are source files
+SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
+DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
+
 default: run
 
 profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
@@ -25,6 +39,7 @@ run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
 	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) 2>&1 > $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log
 	echo "Please check $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
 	
+
 wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE)
 	verilator \
 	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
@@ -34,16 +49,18 @@ wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE)
 	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
 	${WALLY}/sim/verilator/wrapper.c \
 	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+
 	
-obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
+obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_profiling
 	verilator \
 	--Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \
 	--binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
+	$(INCLUDE_PATH) \
 	wrapper.c \
-	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+	$(SOURCES)
 
 questa:
 	vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index 7350eac9c..5bb82f642 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -26,6 +26,12 @@
 
 // This model actually works correctly with vivado.
 
+`ifdef VERILATOR
+import "DPI-C" function string getenvval(input string env_name);
+`else
+import "DPI-C" function string getenv(input string env_name);
+`endif
+
 module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
   (input  logic                  clk,
    input  logic                  ce,
@@ -48,7 +54,11 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
 
   initial begin
     if (PRELOAD_ENABLED) begin
+`ifdef VERILATOR
+      $readmemh({getenvval("WALLY"), "/fpga/src/boot.mem"}, ROM, 0);
+`else
       $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0);
+`endif
     end
   end
   
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index cf87222c3..b74827165 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -39,7 +39,6 @@ import "DPI-C" function string getenvval(input string env_name);
 `else
 import "DPI-C" function string getenv(input string env_name);
 `endif
-import "DPI-C" function int system(input string env_name);
 
 module testbench;
   /* verilator lint_off WIDTHTRUNC */
@@ -254,8 +253,9 @@ module testbench;
   logic        ResetCntRst;
   logic        CopyRAM;
 
-  string  signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
+  string  signame, memfilename, bootmemfilename, uartoutfilename, pathname;
   integer begin_signature_addr, end_signature_addr, signature_size;
+  integer uartoutfile;
 
   assign ResetThreshold = 3'd5;
 
@@ -328,8 +328,6 @@ module testbench;
   else
     assign EcallFaultM = 0;
   
-  // this is an unused integer for the return value of `system`
-  int unused_int;
   always @(posedge clk) begin
     ////////////////////////////////////////////////////////////////////////////////
     // Verify the test ran correctly by checking the memory against a known signature.
@@ -355,8 +353,7 @@ module testbench;
         memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
         bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
         uartoutfilename = {"logs/", TEST, "_uart.out"};
-        rmCmd = {"rm -f ", uartoutfilename};
-        unused_int = system(rmCmd); // Delete existing UARToutfile
+        uartoutfile = $fopen(uartoutfilename, "wb");
       end
       else            memfilename = {pathname, tests[test], ".elf.memfile"};
       if (riscofTest) begin
@@ -383,6 +380,8 @@ module testbench;
   always @(posedge Validate) // added
 `endif
     if(Validate) begin
+      if (TEST == "buildroot")
+        $fclose(uartoutfile);
       if (TEST == "embench") begin
         // Writes contents of begin_signature to .sim.output file
         // this contains instret and cycles for start and end of test run, used by embench 
@@ -602,9 +601,7 @@ module testbench;
     always @(posedge clk) begin
       if (TEST == "buildroot") begin
         if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
-          memFile = $fopen(uartoutfilename, "ab");
-          $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
-          $fclose(memFile);
+          $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
         end
       end
     end