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https://github.com/openhwgroup/cvw
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working testbench-imperas
This commit is contained in:
Shriya Nadgauda
parent
0be6b81df9
commit
c10d332c6e
@ -29,8 +29,7 @@
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module testbench();
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parameter DEBUG = 0;
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parameter TESTSBP = 0;
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parameter TESTSPERIPH = 0 ; // set to 0 for regression
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localparam MAXSIGLEN = 1000000;
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parameter TESTSPERIPH = 0; // set to 0 for regression
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logic clk;
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logic reset;
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@ -38,8 +37,8 @@ module testbench();
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parameter SIGNATURESIZE = 5000000;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:MAXSIGLEN];
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logic [`XLEN-1:0] signature[0:MAXSIGLEN];
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logic [31:0] sig32[0:SIGNATURESIZE];
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logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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@ -55,71 +54,7 @@ module testbench();
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string tests64f[] = '{
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"rv64f/I-FADD-S-01", "2000",
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"rv64f/I-FCLASS-S-01", "2000",
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"rv64f/I-FCVT-S-L-01", "2000",
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"rv64f/I-FCVT-S-LU-01", "2000",
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"rv64f/I-FCVT-S-W-01", "2000",
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"rv64f/I-FCVT-S-WU-01", "2000",
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"rv64f/I-FCVT-L-S-01", "2000",
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"rv64f/I-FCVT-LU-S-01", "2000",
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"rv64f/I-FCVT-W-S-01", "2000",
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"rv64f/I-FCVT-WU-S-01", "2000",
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"rv64f/I-FDIV-S-01", "2000",
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"rv64f/I-FEQ-S-01", "2000",
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"rv64f/I-FLE-S-01", "2000",
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"rv64f/I-FLT-S-01", "2000",
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"rv64f/I-FMADD-S-01", "2000",
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"rv64f/I-FMAX-S-01", "2000",
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"rv64f/I-FMIN-S-01", "2000",
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"rv64f/I-FMSUB-S-01", "2000",
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"rv64f/I-FMUL-S-01", "2000",
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"rv64f/I-FMV-W-X-01", "2000",
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"rv64f/I-FMV-X-W-01", "2000",
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"rv64f/I-FNMADD-S-01", "2000",
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"rv64f/I-FNMSUB-S-01", "2000",
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"rv64f/I-FSGNJ-S-01", "2000",
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"rv64f/I-FSGNJN-S-01", "2000",
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"rv64f/I-FSGNJX-S-01", "2000",
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"rv64f/I-FSQRT-S-01", "2000",
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"rv64f/I-FSW-01", "2000",
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"rv64f/I-FLW-01", "2110",
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"rv64f/I-FSUB-S-01", "2000"
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};
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string tests64d[] = '{
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"rv64d/I-FADD-D-01", "2000",
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"rv64d/I-FCLASS-D-01", "2000",
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"rv64d/I-FCVT-D-L-01", "2000",
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"rv64d/I-FCVT-D-LU-01", "2000",
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"rv64d/I-FCVT-D-S-01", "2000",
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"rv64d/I-FCVT-D-W-01", "2000",
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"rv64d/I-FCVT-D-WU-01", "2000",
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"rv64d/I-FCVT-L-D-01", "2000",
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"rv64d/I-FCVT-LU-D-01", "2000",
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"rv64d/I-FCVT-S-D-01", "2000",
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"rv64d/I-FCVT-W-D-01", "2000",
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"rv64d/I-FCVT-WU-D-01", "2000",
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"rv64d/I-FDIV-D-01", "2000",
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"rv64d/I-FEQ-D-01", "2000",
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"rv64d/I-FLD-D-01", "2420",
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"rv64d/I-FLE-D-01", "2000",
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"rv64d/I-FLT-D-01", "2000",
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"rv64d/I-FMADD-D-01", "2000",
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"rv64d/I-FMAX-D-01", "2000",
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"rv64d/I-FMIN-D-01", "2000",
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"rv64d/I-FMSUB-D-01", "2000",
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"rv64d/I-FMUL-D-01", "2000",
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"rv64d/I-FMV-D-X-01", "2000",
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"rv64d/I-FMV-X-D-01", "2000",
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"rv64d/I-FNMADD-D-01", "2000",
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"rv64d/I-FNMSUB-D-01", "2000",
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"rv64d/I-FSD-01", "2000",
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"rv64d/I-FSGNJ-D-01", "2000",
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"rv64d/I-FSGNJN-D-01", "2000",
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"rv64d/I-FSGNJX-D-01", "2000",
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"rv64d/I-FSQRTD-01", "2000",
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"rv64d/I-FSUB-D-01", "2000"
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"rv64f/I-FCLASS-S-01", "2000"
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};
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string tests64a[] = '{
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@ -327,40 +262,6 @@ module testbench();
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"rv32i/I-MISALIGN_JMP-01","2000"
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};
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string tests32f[] = '{
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"rv32f/I-FADD-S-01", "2000",
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"rv32f/I-FCLASS-S-01", "2000",
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"rv32f/I-FCVT-S-L-01", "2000",
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"rv32f/I-FCVT-S-LU-01", "2000",
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"rv32f/I-FCVT-S-W-01", "2000",
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"rv32f/I-FCVT-S-WU-01", "2000",
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"rv32f/I-FCVT-L-S-01", "2000",
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"rv32f/I-FCVT-LU-S-01", "2000",
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"rv32f/I-FCVT-W-S-01", "2000",
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"rv32f/I-FCVT-WU-S-01", "2000",
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"rv32f/I-FDIV-S-01", "2000",
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"rv32f/I-FEQ-S-01", "2000",
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"rv32f/I-FLE-S-01", "2000",
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"rv32f/I-FLT-S-01", "2000",
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"rv32f/I-FMADD-S-01", "2000",
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"rv32f/I-FMAX-S-01", "2000",
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"rv32f/I-FMIN-S-01", "2000",
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"rv32f/I-FMSUB-S-01", "2000",
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"rv32f/I-FMUL-S-01", "2000",
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"rv32f/I-FMV-W-X-01", "2000",
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"rv32f/I-FMV-X-W-01", "2000",
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"rv32f/I-FNMADD-S-01", "2000",
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"rv32f/I-FNMSUB-S-01", "2000",
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"rv32f/I-FSGNJ-S-01", "2000",
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"rv32f/I-FSGNJN-S-01", "2000",
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"rv32f/I-FSGNJX-S-01", "2000",
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"rv32f/I-FSQRT-S-01", "2000",
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"rv32f/I-FSW-01", "2000",
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"rv32f/I-FLW-01", "2110",
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"rv32f/I-FSUB-S-01", "2000"
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};
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string tests32i[] = {
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"rv32i/WALLY-PIPELINE-100K", "10a800",
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"rv32i/I-ADD-01", "2000",
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@ -447,23 +348,19 @@ string tests32f[] = '{
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};
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string tests64p[] = '{
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"rv64p/WALLY-MCAUSE", "4000",
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"rv64p/WALLY-SCAUSE", "3000",
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"rv64p/WALLY-MCAUSE", "2000",
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"rv64p/WALLY-SCAUSE", "2000",
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"rv64p/WALLY-MEPC", "5000",
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"rv64p/WALLY-SEPC", "4000",
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"rv64p/WALLY-MTVAL", "6000",
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"rv64p/WALLY-STVAL", "4000",
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"rv64p/WALLY-MTVEC", "2000",
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"rv64p/WALLY-MARCHID", "4000",
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"rv64p/WALLY-MIMPID", "4000",
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"rv64p/WALLY-MHARTID", "4000",
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"rv64p/WALLY-MVENDORID", "4000",
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"rv64p/WALLY-MIE", "3000",
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"rv64p/WALLY-MEDELEG", "4000"
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"rv64p/WALLY-MVENDORID", "4000"
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};
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string tests32p[] = '{
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<<<<<<< HEAD
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// "rv32p/WALLY-MCAUSE", "2000",
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// "rv32p/WALLY-SCAUSE", "2000",
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// "rv32p/WALLY-MEPC", "5000",
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@ -474,20 +371,6 @@ string tests32f[] = '{
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// "rv32p/WALLY-MIMPID", "4000",
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// "rv32p/WALLY-MHARTID", "4000",
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// "rv32p/WALLY-MVENDORID", "4000"
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=======
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"rv32p/WALLY-MCAUSE", "4000",
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"rv32p/WALLY-SCAUSE", "3000",
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"rv32p/WALLY-MEPC", "5000",
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"rv32p/WALLY-SEPC", "4000",
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"rv32p/WALLY-MTVAL", "5000",
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"rv32p/WALLY-STVAL", "4000",
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"rv32p/WALLY-MARCHID", "4000",
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"rv32p/WALLY-MIMPID", "4000",
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"rv32p/WALLY-MHARTID", "4000",
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"rv32p/WALLY-MVENDORID", "4000"
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//"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
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//"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
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>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
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};
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string tests64periph[] = '{
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@ -542,7 +425,7 @@ string tests32f[] = '{
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if (TESTSPERIPH) begin
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tests = tests32periph;
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end else begin
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tests = {tests32i, tests32p, tests32periph};
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tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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else tests = {tests, tests32iNOc};
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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@ -619,11 +502,7 @@ string tests32f[] = '{
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$display("Code ended with ecall with gp = 1");
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#60; // give time for instructions in pipeline to finish
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// clear signature to prevent contamination from previous tests
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<<<<<<< HEAD
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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=======
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for(i=0; i<MAXSIGLEN; i=i+1) begin
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>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
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sig32[i] = 'bx;
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end
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@ -631,11 +510,7 @@ string tests32f[] = '{
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signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
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$readmemh(signame, sig32);
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i = 0;
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<<<<<<< HEAD
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while (i < SIGNATURESIZE) begin
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=======
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while (i < MAXSIGLEN) begin
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>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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@ -740,13 +615,11 @@ module instrNameDecTB(
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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logic [4:0] rs2;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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assign rs2 = instr[24:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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@ -870,67 +743,6 @@ module instrNameDecTB(
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else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
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else name = "ILLEGAL";
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10'b0001111_???: name = "FENCE";
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10'b1000011_???: name = "FMADD";
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10'b1000111_???: name = "FMSUB";
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10'b1001011_???: name = "FNMSUB";
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10'b1001111_???: name = "FNMADD";
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10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
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else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
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else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
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else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE
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else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE
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else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
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else if (funct7[6:2] == 5'b00101) name = "FMIN";
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else if (funct7[6:2] == 5'b10100) name = "FLE";
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else name = "ILLEGAL";
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10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
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else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
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else if (funct7[6:2] == 5'b00101) name = "FMAX";
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else if (funct7[6:2] == 5'b10100) name = "FLT";
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else if (funct7[6:2] == 5'b11100) name = "FCLASS";
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else name = "ILLEGAL";
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10'b0101111_010: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
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else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
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else if (funct7[6:2] == 5'b10100) name = "FEQ";
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else name = "ILLEGAL";
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10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
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else name = "ILLEGAL";
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10'b0000111_010: name = "FLW";
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10'b0100111_010: name = "FSW";
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10'b0000111_010: name = "FLD";
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10'b0100111_010: name = "FSD";
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default: name = "ILLEGAL";
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endcase
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endmodule
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