diff --git a/config/derivlist.txt b/config/derivlist.txt index 32768a3af..6063d5923 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -327,23 +327,23 @@ INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc INSTR_CLASS_PRED 0 diff --git a/sim/regression-wally b/sim/regression-wally index ba42a1d7f..d06ac0b28 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -72,7 +72,7 @@ def getBuildrootTC(boot): BRcmd="vsim > {} -c < {} -c < {} -c <= 4 and test[2] == "configOptions"): configOptions = test[3] - cmdPrefix = "vsim > {} -c < {} -c < {} -c < $argc} break + set arg [expr "$$x"] + lappend lst $arg +} + if {$argc >= 3} { if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { set coverage 1 + set CoverageVoptArg "+cover=sbecf" + set CoverageVsimArg "-coverage" + } elseif {$3 eq "configOptions"} { + set configOptions $lst + puts $configOptions } } @@ -51,47 +65,20 @@ if {$argc >= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc -if {$2 eq "configOptions"} { - # set arguments " " - # for {set i 5} {$i <= $argc} {incr i} { - # append arguments "\$$i " - # } - # puts $arguments - # set options eval $arguments - # **** fix this so we can pass any number of +defines or top level params. - # only allows 1 right now - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 - # start and run simulation - # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$3 ${4} -o testbenchopt - vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 - # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time - #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf - #vsim -coverage -lib work_$2 workopt_$2 - # power add generates the logging necessary for said generation. - # power add -r /dut/core/* - run -all - # power off -r /dut/core/* +vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} +vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg} -} else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 - # start and run simulation - # remove +acc flag for faster sim during regressions if there is no need to access internal signals - if {$coverage} { -# vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf - vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage - } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 - } # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 - # power add generates the logging necessary for said generation. - # power add -r /dut/core/* - run -all - # power off -r /dut/core/* -} +# power add generates the logging necessary for said generation. +# power add -r /dut/core/* +run -all +# power off -r /dut/core/* + if {$coverage} { echo "Saving coverage to ${1}_${2}.ucdb" diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do index e9bad30d5..1165676a0 100644 --- a/sim/wally-linux-imperas.do +++ b/sim/wally-linux-imperas.do @@ -32,25 +32,10 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 - - #-- Run the Simulation - #run -all - run 7000 ms - add log -recursive /* - do linux-wave.do - run -all - - exec ./slack-notifier/slack-notifier.py - -} elseif {$2 eq "buildroot-no-trace"} { +if {$2 eq "buildroot"} { vlog -lint -work work_${1}_${2} \ +define+USE_IMPERAS_DV \ - +incdir+../config/$1 \ + +incdir+../config/deriv/$1 \ +incdir+../config/shared \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ @@ -64,7 +49,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ ../src/cvw.sv \ - ../testbench/testbench-linux-imperas.sv \ + ../testbench/testbench.sv \ ../testbench/common/*.sv ../src/*/*.sv \ ../src/*/*/*.sv -suppress 2583 @@ -76,7 +61,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { # visualizer -fprofile+perf+dir=fprofile # eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \ - -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt + -G TEST=$2 -o testbenchopt eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ $env(OTHERFLAGS) @@ -96,60 +81,4 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { exec ./slack-notifier/slack-notifier.py -} elseif {$2 eq "fpga"} { - echo "hello" - vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 - vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt - vsim workopt +nowarn3829 -fatal 7 - - do fpga-wave.do - add log -r /* - run 20 ms - -} else { - if {$2 eq "ahb"} { - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 - } else { - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 - } - vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt - - vsim workopt +nowarn3829 -fatal 7 - - view wave - #-- display input and output signals as hexidecimal values - #do ./wave-dos/peripheral-waves.do - add log -recursive /* - do wave.do - #do wave-bus.do - - # power add generates the logging necessary for saif generation. - #power add -r /dut/core/* - #-- Run the Simulation - - run -all - #power off -r /dut/core/* - #power report -all -bsaif power.saif - noview ../testbench/testbench.sv - view wave } - - - -#elseif {$2 eq "buildroot-no-trace""} { -# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation -# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt -# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 - - #-- Run the Simulation -# run 100 ns -# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa -# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 -# add log -recursive /* -# do linux-wave.do -# run -all - -# exec ./slack-notifier/slack-notifier.py -#} diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv deleted file mode 100644 index 8f22b82a7..000000000 --- a/testbench/testbench-linux-imperas.sv +++ /dev/null @@ -1,1050 +0,0 @@ -/////////////////////////////////////////// -// testbench-linux.sv -// -// Written: nboorstin@g.hmc.edu 2021 -// Modified: -// -// Purpose: Testbench for Buildroot Linux -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "config.vh" -`include "BranchPredictorType.vh" - -// This is set from the command line script -// `define USE_IMPERAS_DV - -`ifdef USE_IMPERAS_DV - `include "idv/idv.svh" -`endif - -import cvw::*; - -`define DEBUG_TRACE 0 -// Debug Levels -// 0: don't check against QEMU -// 1: print disagreements with QEMU, but only halt on PCW disagreements -// 2: halt on any disagreement with QEMU except CSRs -// 3: halt on all disagreements with QEMU -// 4: print memory accesses whenever they happen -// 5: print everything - -module testbench; - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////// CONFIG //////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Recommend setting all of these in 'do' script using -G option - parameter INSTR_LIMIT = 0; // # of instructions at which to stop - parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim - parameter CHECKPOINT = 0; - parameter RISCV_DIR = "/opt/riscv"; - parameter NO_SPOOFING = 0; - - - `ifdef USE_IMPERAS_DV - import idvPkg::*; - import rvviApiPkg::*; - import idvApiPkg::*; - `endif - - - `include "parameter-defs.vh" - - - - //////////////////////////////////////////////////////////////////////////////////// - //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// - //////////////////////////////////////////////////////////////////////////////////// - // ========== Testbench Core ========== - integer warningCount = 0; - integer errorCount = 0; - integer fault; - string ProgramAddrMapFile, ProgramLabelMapFile; - // ========== Initialization ========== - string testvectorDir; - string linuxImageDir; - integer memFile; - integer readResult; - // ========== Checkpointing ========== - string checkpointDir; - logic [1:0] initPriv; - // ========== Trace parsing & checking ========== - integer garbageInt; - string garbageString; - `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ - integer traceFile``STAGE; \ - integer matchCount``STAGE; \ - string line``STAGE; \ - string token``STAGE; \ - string ExpectedTokens``STAGE [31:0]; \ - integer index``STAGE; \ - integer StartIndex``STAGE, EndIndex``STAGE; \ - integer TokenIndex``STAGE; \ - integer MarkerIndex``STAGE; \ - integer NumCSR``STAGE; \ - logic [P.XLEN-1:0] ExpectedPC``STAGE; \ - logic [31:0] ExpectedInstr``STAGE; \ - string text``STAGE; \ - string MemOp``STAGE; \ - string RegWrite``STAGE; \ - integer ExpectedRegAdr``STAGE; \ - logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \ - logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ - string ExpectedCSRArray``STAGE[10:0]; \ - logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? - `DECLARE_TRACE_SCANNER_SIGNALS(E) - `DECLARE_TRACE_SCANNER_SIGNALS(M) - // M-stage expected values - logic checkInstrM; - integer MIPexpected, SIPexpected; - string name; - logic [P.AHBW-1:0] readDataExpected; - // W-stage expected values - logic checkInstrW; - logic [P.XLEN-1:0] ExpectedPCW; - logic [31:0] ExpectedInstrW; - string textW; - string RegWriteW; - integer ExpectedRegAdrW; - logic [P.XLEN-1:0] ExpectedRegValueW; - string MemOpW; - logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; - integer NumCSRW; - string ExpectedCSRArrayW[10:0]; - logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0]; - logic [P.XLEN-1:0] ExpectedIntType; - integer NumCSRWIndex; - integer NumCSRPostWIndex; - logic [P.XLEN-1:0] InstrCountW; - // ========== Interrupt parsing & spoofing ========== - string interrupt; - string interruptLine; - integer interruptFile; - integer interruptInstrCount; - integer interruptHartVal; - integer interruptAsyncVal; - longint interruptCauseVal; - longint interruptEpcVal; - longint interruptTVal; - string interruptDesc; - integer NextMIPexpected, NextSIPexpected; - integer NextMepcExpected; - logic [P.XLEN-1:0] AttemptedInstructionCount; - // ========== Misc Aliases ========== - `define RF dut.core.ieu.dp.regf.rf - `define PC dut.core.ifu.pcreg.q - `define PRIV_BASE dut.core.priv.priv - `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q - `define CSR_BASE `PRIV_BASE.csr - `define MEIP `PRIV_BASE.MExtInt - `define SEIP `PRIV_BASE.SExtInt - `define MTIP `PRIV_BASE.MTimerInt - `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW - `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q - `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.MIE_REGW - `define MIP `CSR_BASE.csri.MIP_REGW_writeable - `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q - `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q - `define MEPC `CSR_BASE.csrm.MEPCreg.q - `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q - `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q - `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q - `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q - `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q - `define MTVEC `CSR_BASE.csrm.MTVECreg.q - `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q - `define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q - `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] - `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW - `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW - `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT - `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT - `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT - `define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT - `define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT - `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT - `define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT - `define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP - `define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP - `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE - `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE - `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE - `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE - `define UART dut.uncore.uncore.uart.uart.u - `define UART_IER `UART.IER - `define UART_LCR `UART.LCR - `define UART_MCR `UART.MCR - `define UART_SCR `UART.SCR - `define UART_IP `UART.INTR - `define PLIC dut.uncore.uncore.plic.plic - `define PLIC_INT_PRIORITY `PLIC.intPriority - `define PLIC_INT_ENABLE `PLIC.intEn - `define PLIC_THRESHOLD `PLIC.intThreshold - `define PCM dut.core.ifu.PCM - // ========== COMMON MACROS ========== - // Needed for initialization and core - `define SCAN_NEW_INTERRUPT \ - begin \ - $fgets(interruptLine, interruptFile); \ - //$display("Time %t, interruptLine %x", $time, interruptLine); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptInstrCount); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptHartVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptAsyncVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptCauseVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptEpcVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptTVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%s", interruptDesc); \ - end - - - - - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - ////////////////////////////////// HARDWARE /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Clock and Reset - logic clk, reset_ext; - logic reset; - initial begin reset_ext <= 1; # 22; reset_ext <= 0; end - always begin clk <= 1; # 5; clk <= 0; # 5; end - // Wally Interface - logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic HCLK, HRESETn; - logic HREADY; - logic HSELEXT; - logic HSELEXTSDC; - logic [P.PA_BITS-1:0] HADDR; - logic [P.AHBW-1:0] HWDATA; - logic [P.XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic [31:0] GPIOIN; - logic [31:0] GPIOOUT, GPIOEN; - logic UARTSin, UARTSout; - - // FPGA-specific Stuff - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - logic SDCIntr; - logic SPIIn, SPIOut; - logic [3:0] SPICS; - - - // Hardwire UART, GPIO pins - assign GPIOIN = 0; - assign UARTSin = 1; - assign SDCIntr = 0; - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// Cache Issue /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - - // Duplicate copy of pipeline registers that are optimized out of some configurations - logic [31:0] NextInstrE, InstrM; - mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE); - flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM); - - logic probe; - if (NO_SPOOFING) - assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c - & InstrM != 32'h14021273 - & testbench.dut.core.InstrValidM; - - - `ifdef USE_IMPERAS_DV - - logic DCacheFlushDone, DCacheFlushStart; - - rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); - wallyTracer #(P) wallyTracer(rvvi); - - trace2log idv_trace2log(rvvi); -// trace2cov idv_trace2cov(rvvi); - - // enabling of comparison types - trace2api #(.CMP_PC (1), - .CMP_INS (1), - .CMP_GPR (1), - .CMP_FPR (1), - .CMP_VR (0), - .CMP_CSR (1) - ) idv_trace2api(rvvi); - - initial begin - int iter; - #1; - IDV_MAX_ERRORS = 3; - - // Initialize REF (do this before initializing the DUT) - if (!rvviVersionCheck(RVVI_API_VERSION)) begin - $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); - $fatal; - end - - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); - void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); - void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); - - if (!rvviRefInit("")) begin - $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); - $fatal; - end - - // Volatile CSRs - void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE - void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE - void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET - void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET - void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME - - // User HPMCOUNTER3 - HPMCOUNTER31 - for (iter='hC03; iter<='hC1F; iter++) begin - void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx - end - - // Machine MHPMCOUNTER3 - MHPMCOUNTER31 - for (iter='hB03; iter<='hB1F; iter++) begin - void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx - end - - // cannot predict this register due to latency between - // pending and taken - void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP - void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP - - // Privileges for PMA are set in the imperas.ic - // volatile (IO) regions are defined here - // only real ROM/RAM areas are BOOTROM and UNCORE_RAM - if (P.CLINT_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE))); - end - if (P.GPIO_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE))); - end - if (P.UART_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE))); - end - if (P.PLIC_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE))); - end - if (P.SDC_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE))); - end - if (P.SPI_SUPPORTED) begin - void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE))); - end - - if(P.XLEN==32) begin - void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH - void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH - void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH - void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH - end - - void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! - - // Load memory - begin - longint x64; - int x32[2]; - longint index; - - $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); - - $display("RVVI Loading bootmem.bin"); - memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); - index = 'h1000 - 8; - while(!$feof(memFile)) begin - index+=8; - readResult = $fread(x64, memFile); - if (x64 == 0) continue; - x32[0] = x64 & 'hffffffff; - x32[1] = x64 >> 32; - rvviRefMemoryWrite(0, index+0, x32[0], 4); - rvviRefMemoryWrite(0, index+4, x32[1], 4); - //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); - end - $fclose(memFile); - - $display("RVVI Loading ram.bin"); - memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); - index = 'h80000000 - 8; - while(!$feof(memFile)) begin - index+=8; - readResult = $fread(x64, memFile); - if (x64 == 0) continue; - x32[0] = x64 & 'hffffffff; - x32[1] = x64 >> 32; - rvviRefMemoryWrite(0, index+0, x32[0], 4); - rvviRefMemoryWrite(0, index+4, x32[1], 4); - //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); - end - $fclose(memFile); - - $display("RVVI Loading Complete"); - - void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address - end - end - - always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5])); - - final begin - void'(rvviRefShutdown()); - end - - `endif - - - // Wally - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); - - // W-stage hardware not needed by Wally itself - parameter nop = 'h13; - logic [P.XLEN-1:0] PCW; - logic [31:0] InstrW; - logic InstrValidW; - logic [P.XLEN-1:0] IEUAdrW, WriteDataW; - logic TrapW; - `define FLUSHW dut.core.FlushW - `define STALLW dut.core.StallW - flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : InstrM, InstrW); - flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); - flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); - flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// INITIALIZATION //////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // ========== CHECKPOINTING ========== - `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - initial begin \ - #1; \ - if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ - end - - `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - initial begin \ - if (CHECKPOINT!=0) begin \ - force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - while (reset!==1) #1; \ - while (reset!==0) #1; \ - #1; \ - release `SIGNAL; \ - end \ - end - - `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - for (i=ARRAY_MIN; i= 2)) fault = 1; \ - end - - `define checkCSR(CSR) \ - begin \ - if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ - $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ - end \ - end - - // =========== CORE =========== - assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; - always @(negedge clk) begin - `SCAN_NEW_INSTR_FROM_TRACE(E) - `SCAN_NEW_INSTR_FROM_TRACE(M) - end - - // step 1: register expected state into the write back stage. - always @(posedge clk) begin - if (reset) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if(~dut.core.StallW) begin - if(dut.core.FlushW) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if (dut.core.ieu.c.InstrValidM) begin - ExpectedPCW <= ExpectedPCM; - ExpectedInstrW <= ExpectedInstrM; - textW <= textM; - RegWriteW <= RegWriteM; - ExpectedRegAdrW <= ExpectedRegAdrM; - ExpectedRegValueW <= ExpectedRegValueM; - ExpectedIEUAdrW <= ExpectedIEUAdrM; - MemOpW <= MemOpM; - ExpectedMemWriteDataW <= ExpectedMemWriteDataM; - ExpectedMemReadDataW <= ExpectedMemReadDataM; - NumCSRW <= NumCSRM; - for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin - ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; - ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; - end - end - #1; - // override on special conditions - if(~dut.core.StallW) begin - if(textW.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_SPOOFING) - release dut.uncore.uncore.clint.clint.MTIME; - end - //if (ExpectedIEUAdrM == 'h10000005) begin - //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); - //release dut.core.ieu.dp.ReadDataM; - //end - end - end - end - - // step2: make all checks in the write back stage. - assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. - always @(negedge clk) begin - #1; // small delay allows interrupt spoofing to happen first - // always check PC, instruction bits - if (checkInstrW) begin - InstrCountW += 1; - // print progress message - if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); - // turn on waves - if (AttemptedInstructionCount == INSTR_WAVEON) $stop; - // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end - fault = 0; - if (`DEBUG_TRACE >= 1) begin - `checkEQ("PCW",PCW,ExpectedPCW) - //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of - // compressed to uncompressed conversion - `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) - #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin - $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); - $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); - end - if (RegWriteW == "GPR") begin - `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) - $sformat(name,"RF[%02d]",ExpectedRegAdrW); - `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) - end - if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); - `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); - `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); - `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) - end - end - // check csr - for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin - case(ExpectedCSRArrayW[NumCSRPostWIndex]) - "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) - "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) - "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) - "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) - "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) - "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) - "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) - "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) - "menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW) - "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) - "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) - "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) - "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) - // "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // *** fix me - "mip": begin - `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_SPOOFING) begin - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) - force `MEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) - force `SEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) - force `UART_IP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) - force `MTIP = 0; - end - end - endcase - end - if (fault == 1) begin - errorCount +=1; - $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; $stop; - end - end // if (`DEBUG_TRACE >= 1) - end // if (checkInstrW) - end // always @ (negedge clk) - - - // New IP spoofing - logic globalIntsBecomeEnabled; - assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); - logic checkInterruptM; - assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; - - always @(negedge clk) begin - if(checkInterruptM) begin - if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_SPOOFING) begin - case (interruptCauseVal) - 11: begin - force `MEIP = 1; - force `UART_IP = 1; - end - 09: begin - force `SEIP = 1; - force `UART_IP = 1; - end - 07: force `MTIP = 1; - default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); - endcase - $display("Forcing interrupt."); - end - `SCAN_NEW_INTERRUPT - if (globalIntsBecomeEnabled) begin - $display("Enabled global interrupts"); - // The idea here is if a CSR instruction causes an interrupt by - // enabling interrupts, that CSR instruction will commit. - end else begin - // Other instructions, however, will get interrupted and not - // commit, so we don't want our W-stage checker to look for them - // and get confused when it doesn't find them. - garbageInt = $fgets(garbageString,traceFileE); - garbageInt = $fgets(garbageString,traceFileM); - AttemptedInstructionCount += 1; - end - end - end - end - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - //////////////////////////////// Extra Features /////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Function Tracking - FunctionName #(P) FunctionName(.reset(reset), - .clk(clk), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - - // Instr Opcode Tracking - // For waveview convenience - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.InstrRawF[31:0], - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // ------------------ - // Address Translator - // ------------------ - /** - * Walk the page table stored in ram according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - logic SvMode, PTE_R, PTE_X; - logic [P.XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [2:0]; - logic [11:0] Offset; - function logic [P.XLEN-1:0] adrTranslator( - input logic [P.XLEN-1:0] adrIn); - begin - int i; - // Grab the SATP register from privileged unit - SATP = dut.core.priv.priv.csr.SATP_REGW; - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - // We do not support sv48; only sv39 - SvMode = SATP[63]; - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R | PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction -endmodule diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv deleted file mode 100644 index 011c4d148..000000000 --- a/testbench/testbench-linux.sv +++ /dev/null @@ -1,870 +0,0 @@ -/////////////////////////////////////////// -// testbench-linux.sv -// -// Written: nboorstin@g.hmc.edu 2021 -// Modified: -// -// Purpose: Testbench for Buildroot Linux -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "config.vh" -import cvw::*; - -`define DEBUG_TRACE 0 -// Debug Levels -// 0: don't check against QEMU -// 1: print disagreements with QEMU, but only halt on PCW disagreements -// 2: halt on any disagreement with QEMU except CSRs -// 3: halt on all disagreements with QEMU -// 4: print memory accesses whenever they happen -// 5: print everything - -module testbench; - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////// CONFIG //////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Recommend setting all of these in 'do' script using -G option - parameter INSTR_LIMIT = 0; // # of instructions at which to stop - parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim - parameter CHECKPOINT = 0; - parameter RISCV_DIR = "/opt/riscv"; - parameter NO_SPOOFING = 0; - - -`include "parameter-defs.vh" - - - //////////////////////////////////////////////////////////////////////////////////// - //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// - //////////////////////////////////////////////////////////////////////////////////// - // ========== Testbench Core ========== - integer warningCount = 0; - integer errorCount = 0; - integer fault; - string ProgramAddrMapFile, ProgramLabelMapFile; - // ========== Initialization ========== - string testvectorDir; - string linuxImageDir; - integer memFile; - integer readResult; - // ========== Checkpointing ========== - string checkpointDir; - logic [1:0] initPriv; - // ========== Trace parsing & checking ========== - integer garbageInt; - string garbageString; - `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ - integer traceFile``STAGE; \ - integer matchCount``STAGE; \ - string line``STAGE; \ - string token``STAGE; \ - string ExpectedTokens``STAGE [31:0]; \ - integer index``STAGE; \ - integer StartIndex``STAGE, EndIndex``STAGE; \ - integer TokenIndex``STAGE; \ - integer MarkerIndex``STAGE; \ - integer NumCSR``STAGE; \ - logic [P.XLEN-1:0] ExpectedPC``STAGE; \ - logic [31:0] ExpectedInstr``STAGE; \ - string text``STAGE; \ - string MemOp``STAGE; \ - string RegWrite``STAGE; \ - integer ExpectedRegAdr``STAGE; \ - logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \ - logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ - string ExpectedCSRArray``STAGE[10:0]; \ - logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? - `DECLARE_TRACE_SCANNER_SIGNALS(E) - `DECLARE_TRACE_SCANNER_SIGNALS(M) - // M-stage expected values - logic checkInstrM; - integer MIPexpected, SIPexpected; - string name; - logic [P.AHBW-1:0] readDataExpected; - // W-stage expected values - logic checkInstrW; - logic [P.XLEN-1:0] ExpectedPCW; - logic [31:0] ExpectedInstrW; - string textW; - string RegWriteW; - integer ExpectedRegAdrW; - logic [P.XLEN-1:0] ExpectedRegValueW; - string MemOpW; - logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; - integer NumCSRW; - string ExpectedCSRArrayW[10:0]; - logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0]; - logic [P.XLEN-1:0] ExpectedIntType; - integer NumCSRWIndex; - integer NumCSRPostWIndex; - logic [P.XLEN-1:0] InstrCountW; - // ========== Interrupt parsing & spoofing ========== - string interrupt; - string interruptLine; - integer interruptFile; - integer interruptInstrCount; - integer interruptHartVal; - integer interruptAsyncVal; - longint interruptCauseVal; - longint interruptEpcVal; - longint interruptTVal; - string interruptDesc; - integer NextMIPexpected, NextSIPexpected; - integer NextMepcExpected; - logic [P.XLEN-1:0] AttemptedInstructionCount; - // ========== Misc Aliases ========== - `define RF dut.core.ieu.dp.regf.rf - `define PC dut.core.ifu.pcreg.q - `define PRIV_BASE dut.core.priv.priv - `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q - `define CSR_BASE `PRIV_BASE.csr - `define MEIP `PRIV_BASE.MExtInt - `define SEIP `PRIV_BASE.SExtInt - `define MTIP `PRIV_BASE.MTimerInt - `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW - `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q - `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.MIE_REGW - `define MIP `CSR_BASE.csri.MIP_REGW_writeable - `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q - `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q - `define MEPC `CSR_BASE.csrm.MEPCreg.q - `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q - `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q - `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q - `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q - `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q - `define MTVEC `CSR_BASE.csrm.MTVECreg.q - `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q - `define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q - `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] - `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW - `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW - `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT - `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT - `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT - `define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT - `define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT - `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT - `define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT - `define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP - `define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP - `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE - `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE - `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE - `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE - `define UART dut.uncore.uncore.uart.uart.u - `define UART_IER `UART.IER - `define UART_LCR `UART.LCR - `define UART_MCR `UART.MCR - `define UART_SCR `UART.SCR - `define UART_IP `UART.INTR - `define PLIC dut.uncore.uncore.plic.plic - `define PLIC_INT_PRIORITY `PLIC.intPriority - `define PLIC_INT_ENABLE `PLIC.intEn - `define PLIC_THRESHOLD `PLIC.intThreshold - `define PCM dut.core.ifu.PCM - // ========== COMMON MACROS ========== - // Needed for initialization and core - `define SCAN_NEW_INTERRUPT \ - begin \ - $fgets(interruptLine, interruptFile); \ - //$display("Time %t, interruptLine %x", $time, interruptLine); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptInstrCount); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptHartVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptAsyncVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptCauseVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptEpcVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptTVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%s", interruptDesc); \ - end - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// Cache Issue /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - - // Duplicate copy of pipeline registers that are optimized out of some configurations - logic [31:0] NextInstrE, InstrM; - mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE); - flopenr #(32) InstrMReg(dut.core.clk, dut.core.reset, ~dut.core.ifu.StallM, NextInstrE, InstrM); - - logic probe; - if (NO_SPOOFING) - assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c - & InstrM != 32'h14021273 - & testbench.dut.core.InstrValidM; - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - ////////////////////////////////// HARDWARE /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Clock and Reset - logic clk, reset_ext; - logic reset; - initial begin reset_ext <= 1; # 22; reset_ext <= 0; end - always begin clk <= 1; # 5; clk <= 0; # 5; end - // Wally Interface - logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic HCLK, HRESETn; - logic HREADY; - logic HSELEXT; - logic HSELEXTSDC; - logic [P.PA_BITS-1:0] HADDR; - logic [P.AHBW-1:0] HWDATA; - logic [P.XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic [31:0] GPIOIN; - logic [31:0] GPIOOUT, GPIOEN; - logic UARTSin, UARTSout; - logic SPIIn, SPIOut; - logic [3:0] SPICS; - - // FPGA-specific Stuff - logic SDCIntr; - - // Hardwire UART, GPIO pins - assign GPIOIN = 0; - assign UARTSin = 1; - assign SDCIntr = 0; - - // Wally - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); - - // W-stage hardware not needed by Wally itself - parameter nop = 'h13; - logic [P.XLEN-1:0] PCW; - logic [31:0] InstrW; - logic InstrValidW; - logic [P.XLEN-1:0] IEUAdrW, WriteDataW; - logic TrapW; - `define FLUSHW dut.core.FlushW - `define STALLW dut.core.StallW - flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : InstrM, InstrW); - flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); - flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); - flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// INITIALIZATION //////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // ========== CHECKPOINTING ========== - `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - initial begin \ - #1; \ - if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ - end - - `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - initial begin \ - if (CHECKPOINT!=0) begin \ - force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - while (reset!==1) #1; \ - while (reset!==0) #1; \ - #1; \ - release `SIGNAL; \ - end \ - end - - `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - for (i=ARRAY_MIN; i= 2)) fault = 1; \ - end - - `define checkCSR(CSR) \ - begin \ - if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ - $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ - end \ - end - - // =========== CORE =========== - assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; - always @(negedge clk) begin - `SCAN_NEW_INSTR_FROM_TRACE(E) - `SCAN_NEW_INSTR_FROM_TRACE(M) - end - - // step 1: register expected state into the write back stage. - always @(posedge clk) begin - if (reset) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if(~dut.core.StallW) begin - if(dut.core.FlushW) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if (dut.core.ieu.c.InstrValidM) begin - ExpectedPCW <= ExpectedPCM; - ExpectedInstrW <= ExpectedInstrM; - textW <= textM; - RegWriteW <= RegWriteM; - ExpectedRegAdrW <= ExpectedRegAdrM; - ExpectedRegValueW <= ExpectedRegValueM; - ExpectedIEUAdrW <= ExpectedIEUAdrM; - MemOpW <= MemOpM; - ExpectedMemWriteDataW <= ExpectedMemWriteDataM; - ExpectedMemReadDataW <= ExpectedMemReadDataM; - NumCSRW <= NumCSRM; - for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin - ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; - ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; - end - end - #1; - // override on special conditions - if(~dut.core.StallW) begin - if(textW.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_SPOOFING) - release dut.uncore.uncore.clint.clint.MTIME; - end - //if (ExpectedIEUAdrM == 'h10000005) begin - //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); - //release dut.core.ieu.dp.ReadDataM; - //end - end - end - end - - // step2: make all checks in the write back stage. - assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. - always @(negedge clk) begin - #1; // small delay allows interrupt spoofing to happen first - // always check PC, instruction bits - if (checkInstrW) begin - InstrCountW += 1; - // print progress message - if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); - // turn on waves - if (AttemptedInstructionCount == INSTR_WAVEON) $stop; - // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end - fault = 0; - if (`DEBUG_TRACE >= 1) begin - `checkEQ("PCW",PCW,ExpectedPCW) - //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of - // compressed to uncompressed conversion - `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) - #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin - $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); - $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); - end - if (RegWriteW == "GPR") begin - `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) - $sformat(name,"RF[%02d]",ExpectedRegAdrW); - `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) - end - if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); - `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); - `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); - `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) - end - end - // check csr - for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin - case(ExpectedCSRArrayW[NumCSRPostWIndex]) - "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) - "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) - "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) - "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) - "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) - "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) - "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) - "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) - "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) - "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) - "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) - "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) - "mip": begin - `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_SPOOFING) begin - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) - force `MEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) - force `SEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) - force `UART_IP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) - force `MTIP = 0; - end - end - endcase - end - if (fault == 1) begin - errorCount +=1; - $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; $stop; - end - end // if (`DEBUG_TRACE >= 1) - end // if (checkInstrW) - end // always @ (negedge clk) - - - // New IP spoofing - logic globalIntsBecomeEnabled; - assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); - logic checkInterruptM; - assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; - - always @(negedge clk) begin - if(checkInterruptM) begin - if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_SPOOFING) begin - case (interruptCauseVal) - 11: begin - force `MEIP = 1; - force `UART_IP = 1; - end - 09: begin - force `SEIP = 1; - force `UART_IP = 1; - end - 07: force `MTIP = 1; - default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); - endcase - $display("Forcing interrupt."); - end - `SCAN_NEW_INTERRUPT - if (globalIntsBecomeEnabled) begin - $display("Enabled global interrupts"); - // The idea here is if a CSR instruction causes an interrupt by - // enabling interrupts, that CSR instruction will commit. - end else begin - // Other instructions, however, will get interrupted and not - // commit, so we don't want our W-stage checker to look for them - // and get confused when it doesn't find them. - garbageInt = $fgets(garbageString,traceFileE); - garbageInt = $fgets(garbageString,traceFileM); - AttemptedInstructionCount += 1; - end - end - end - end - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - //////////////////////////////// Extra Features /////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Function Tracking - FunctionName #(P) FunctionName(.reset(reset), - .clk(clk), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - - // Instr Opcode Tracking - // For waveview convenience - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.InstrRawF[31:0], - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // ------------------ - // Address Translator - // ------------------ - /** - * Walk the page table stored in ram according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - logic SvMode, PTE_R, PTE_X; - logic [P.XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [2:0]; - logic [11:0] Offset; - function logic [P.XLEN-1:0] adrTranslator( - input logic [P.XLEN-1:0] adrIn); - begin - int i; - // Grab the SATP register from privileged unit - SATP = dut.core.priv.priv.csr.SATP_REGW; - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - // We do not support sv48; only sv39 - SvMode = SATP[63]; - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R | PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction -endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1bd841074..0f8194e62 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -29,6 +29,10 @@ `include "tests.vh" `include "BranchPredictorType.vh" +`ifdef USE_IMPERAS_DV + `include "idv/idv.svh" +`endif + import cvw::*; module testbench; @@ -43,6 +47,12 @@ module testbench; parameter RISCV_DIR = "/opt/riscv"; parameter INSTR_LIMIT = 0; + `ifdef USE_IMPERAS_DV + import idvPkg::*; + import rvviApiPkg::*; + import idvApiPkg::*; + `endif + `include "parameter-defs.vh" logic clk; @@ -540,15 +550,175 @@ module testbench; DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); - if(P.ZICSR_SUPPORTED) begin + if(P.ZICSR_SUPPORTED & INSTR_LIMIT != 0) begin logic [P.XLEN-1:0] Minstret; assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; always @(negedge clk) begin - if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions, %d", Minstret, INSTR_LIMIT); + if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end end +end + + //////////////////////////////////////////////////////////////////////////////// + // ImperasDV Co-simulator hooks + //////////////////////////////////////////////////////////////////////////////// +`ifdef USE_IMPERAS_DV + + rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); + wallyTracer #(P) wallyTracer(rvvi); + + trace2log idv_trace2log(rvvi); + // trace2cov idv_trace2cov(rvvi); + + // enabling of comparison types + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (1), + .CMP_VR (0), + .CMP_CSR (1) + ) idv_trace2api(rvvi); + + initial begin + int iter; + #1; + IDV_MAX_ERRORS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + $fatal; + end + + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); + + if (!rvviRefInit("")) begin + $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + $fatal; + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + // User HPMCOUNTER3 - HPMCOUNTER31 + for (iter='hC03; iter<='hC1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx + end + + // Machine MHPMCOUNTER3 - MHPMCOUNTER31 + for (iter='hB03; iter<='hB1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx + end + + // cannot predict this register due to latency between + // pending and taken + void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP + void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP + + // Privileges for PMA are set in the imperas.ic + // volatile (IO) regions are defined here + // only real ROM/RAM areas are BOOTROM and UNCORE_RAM + if (P.CLINT_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE))); + end + if (P.GPIO_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE))); + end + if (P.UART_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE))); + end + if (P.PLIC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE))); + end + if (P.SDC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE))); + end + if (P.SPI_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE))); + end + + if(P.XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + + void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! + + // Load memory + // *** RT: This section can probably be moved into the same chunk of code which + // loads the memories. However I'm not sure that ImperasDV supports reloading + // the memories without relaunching the simulator. + begin + longint x64; + int x32[2]; + longint index; + string memfilenameImperasDV, bootmemfilenameImperasDV; + + memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"}; + bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + + $display("RVVI Loading bootmem.bin"); + memFile = $fopen(bootmemfilenameImperasDV, "rb"); + index = 'h1000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading ram.bin"); + memFile = $fopen(memfilenameImperasDV, "rb"); + index = 'h80000000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading Complete"); + + void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address + end end + always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5])); + + final begin + void'(rvviRefShutdown()); + end + +`endif + //////////////////////////////////////////////////////////////////////////////// + // END of ImperasDV Co-simulator hooks + //////////////////////////////////////////////////////////////////////////////// + task automatic CheckSignature; // This task must be declared inside this module as it needs access to parameter P. There is // no way to pass P to the task unless we convert it to a module.