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Renamed FinalAMOWriteDataM to AMOWriteDataM

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David Harris 2022-04-18 01:30:03 +00:00
parent 6504017044
commit c07b9d1722
3 changed files with 15 additions and 15 deletions
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4
pipelined/src/lsu/atomic.sv
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@ -41,7 +41,7 @@ module atomic (
input logic [1:0] LSUAtomicM, input logic [1:0] LSUAtomicM,
input logic [1:0] PreLSURWM, input logic [1:0] PreLSURWM,
input logic IgnoreRequest, input logic IgnoreRequest,
output logic [`XLEN-1:0] FinalAMOWriteDataM, output logic [`XLEN-1:0] AMOWriteDataM,
output logic SquashSCW, output logic SquashSCW,
output logic [1:0] LSURWM); output logic [1:0] LSURWM);
@ -50,7 +50,7 @@ module atomic (
amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
.result(AMOResult)); .result(AMOResult));
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM); .SquashSCW, .LSURWM);

8
pipelined/src/lsu/lsu.sv
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@ -181,7 +181,7 @@ module lsu (
// Memory System // Memory System
// Either Data Cache or Data Tightly Integrated Memory or just bus interface // Either Data Cache or Data Tightly Integrated Memory or just bus interface
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; logic [`XLEN-1:0] AMOWriteDataM, FinalWriteDataM;
logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordM;
logic [`XLEN-1:0] ReadDataWordMuxM; logic [`XLEN-1:0] ReadDataWordMuxM;
logic IgnoreRequest; logic IgnoreRequest;
@ -255,13 +255,13 @@ module lsu (
if (`A_SUPPORTED) begin:atomic if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.FinalAMOWriteDataM, .SquashSCW, .LSURWM); .AMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc end else begin:lrsc
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM; assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign AMOWriteDataM = LSUWriteDataM;
end end
subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
.LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM); .LSUFunct3M, .AMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
endmodule endmodule

18
pipelined/src/lsu/subwordwrite.sv
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@ -33,7 +33,7 @@
module subwordwrite ( module subwordwrite (
input logic [2:0] LSUPAdrM, input logic [2:0] LSUPAdrM,
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
input logic [`XLEN-1:0] FinalAMOWriteDataM, input logic [`XLEN-1:0] AMOWriteDataM,
output logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] FinalWriteDataM,
output logic [`XLEN/8-1:0] ByteMaskM output logic [`XLEN/8-1:0] ByteMaskM
); );
@ -46,18 +46,18 @@ module subwordwrite (
if (`XLEN == 64) begin:sww if (`XLEN == 64) begin:sww
always_comb always_comb
case(LSUFunct3M[1:0]) case(LSUFunct3M[1:0])
2'b00: FinalWriteDataM = {8{FinalAMOWriteDataM[7:0]}}; // sb 2'b00: FinalWriteDataM = {8{AMOWriteDataM[7:0]}}; // sb
2'b01: FinalWriteDataM = {4{FinalAMOWriteDataM[15:0]}}; // sh 2'b01: FinalWriteDataM = {4{AMOWriteDataM[15:0]}}; // sh
2'b10: FinalWriteDataM = {2{FinalAMOWriteDataM[31:0]}}; // sw 2'b10: FinalWriteDataM = {2{AMOWriteDataM[31:0]}}; // sw
2'b11: FinalWriteDataM = FinalAMOWriteDataM; // sw 2'b11: FinalWriteDataM = AMOWriteDataM; // sw
endcase endcase
end else begin:sww // 32-bit end else begin:sww // 32-bit
always_comb always_comb
case(LSUFunct3M[1:0]) case(LSUFunct3M[1:0])
2'b00: FinalWriteDataM = {4{FinalAMOWriteDataM[7:0]}}; // sb 2'b00: FinalWriteDataM = {4{AMOWriteDataM[7:0]}}; // sb
2'b01: FinalWriteDataM = {2{FinalAMOWriteDataM[15:0]}}; // sh 2'b01: FinalWriteDataM = {2{AMOWriteDataM[15:0]}}; // sh
2'b10: FinalWriteDataM = FinalAMOWriteDataM; // sw 2'b10: FinalWriteDataM = AMOWriteDataM; // sw
default: FinalWriteDataM = FinalAMOWriteDataM; // shouldn't happen default: FinalWriteDataM = AMOWriteDataM; // shouldn't happen
endcase endcase
end end
endmodule endmodule