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Renamed zero to eq in flag generation

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This commit is contained in:
David Harris 2021-12-19 11:49:15 -08:00
parent e5d2d7a3fd
commit c04c56dae1
2 changed files with 6 additions and 6 deletions
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6
wally-pipelined/src/ieu/comparator.sv
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@ -30,7 +30,7 @@ module comparator #(parameter WIDTH=32) (
output logic [2:0] flags); output logic [2:0] flags);
logic [WIDTH-1:0] bbar, diff; logic [WIDTH-1:0] bbar, diff;
logic carry, zero, neg, overflow, lt, ltu; logic carry, eq, neg, overflow, lt, ltu;
// NOTE: This can be replaced by some faster logic optimized // NOTE: This can be replaced by some faster logic optimized
// to just compute flags and not the difference. // to just compute flags and not the difference.
@ -40,13 +40,13 @@ module comparator #(parameter WIDTH=32) (
assign {carry, diff} = a + bbar + 1; assign {carry, diff} = a + bbar + 1;
// condition code flags based on add/subtract output // condition code flags based on add/subtract output
assign zero = (diff == 0); assign eq = (diff == 0);
assign neg = diff[WIDTH-1]; assign neg = diff[WIDTH-1];
// overflow occurs when the numbers being subtracted have the opposite sign // overflow occurs when the numbers being subtracted have the opposite sign
// and the result has the opposite sign fron the first // and the result has the opposite sign fron the first
assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]); assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
assign lt = neg ^ overflow; assign lt = neg ^ overflow;
assign ltu = ~carry; assign ltu = ~carry;
assign flags = {zero, lt, ltu}; assign flags = {eq, lt, ltu};
endmodule endmodule

6
wally-pipelined/src/ieu/controller.sv
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@ -97,7 +97,7 @@ module controller(
logic SubArithD; logic SubArithD;
logic subD, sraD, sltD, sltuD; logic subD, sraD, sltD, sltuD;
logic BranchTakenE; logic BranchTakenE;
logic zeroE, ltE, ltuE; logic eqE, ltE, ltuE;
logic unused; logic unused;
logic BranchFlagE; logic BranchFlagE;
logic IEURegWriteE; logic IEURegWriteE;
@ -202,8 +202,8 @@ module controller(
{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE}); {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
// Branch Logic // Branch Logic
assign {zeroE, ltE, ltuE} = FlagsE; assign {eqE, ltE, ltuE} = FlagsE;
mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE); mux4 #(1) branchflagmux(eqE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
assign BranchTakenE = BranchFlagE ^ Funct3E[0]; assign BranchTakenE = BranchFlagE ^ Funct3E[0];
assign PCSrcE = JumpE | BranchE & BranchTakenE; assign PCSrcE = JumpE | BranchE & BranchTakenE;