diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 2f581119a..585d3b82a 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -475,7 +475,7 @@ connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/core/ifu/I
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[63]}]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[63]}]]
 
 
 create_debug_port u_ila_0 probe
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index c48e3d2e7..9d1417985 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -64,12 +64,8 @@ module csrc #(parameter
   );
 
   if (`ZICOUNTERS_SUPPORTED) begin:counters
-    (* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
-    logic [63:0] CYCLEPlusM, INSTRETPlusM;
-    logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
-    logic        WriteCYCLEM, WriteINSTRETM;
     logic [4:0]  CounterNumM;
-    logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
+    (* mark_debug = "true" *)     logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
     logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
     logic 			       InstrValidNotFlushedM;
     logic LoadStallE, LoadStallM;