diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index e2be8c7df..4dd4fd29d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -115,21 +115,21 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; logic valid; - int csrid; - + always_comb begin // Since we are detected the CSR change by comparing the old value we need to // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. if(valid) begin // PMPCFG CSRs (space is 0-15 3a0 - 3af) - int inc = P.XLEN == 32 ? 4 : 8; + localparam inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; for (i=0; i