From c028306ba3a29037ab09ead445fbd025576d00ae Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Nov 2022 16:13:31 -0600 Subject: [PATCH] Fixed name change in hptw. --- pipelined/src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index b06814c8a..67a4f2386 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -108,7 +108,7 @@ module hptw ( assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoFlushW, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheStallM; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache