More comments added to abhfsm.

This commit is contained in:
Ross Thompson 2023-01-17 22:58:06 -06:00
parent 36acc91b67
commit c02195301b

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@ -32,15 +32,16 @@ module busfsm (
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
input logic Flush, input logic Stall, // Core pipeline is stalled
input logic [1:0] BusRW, input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic Stall, input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
output logic BusCommitted, output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
output logic BusStall, output logic BusStall, // Bus is busy with an in flight memory operation
output logic CaptureEn, output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
input logic HREADY, // AHB control signals
output logic [1:0] HTRANS, input logic HREADY, // AHB peripheral ready
output logic HWRITE output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ
output logic HWRITE // AHB 0: Read operation 1: Write operation
); );
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype; typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype;