From 1b385c43363c0a4573ebea8a3bec609dc8fefbc2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 May 2023 03:51:59 -0700 Subject: [PATCH 1/5] Changed DIVN comparison from NF to NF+2. Shouldn't make a difference on our word sizes of XLEN=32/64, NF = 10/23/52) but is more proper in the general case. --- config/shared/wally-shared.vh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh index 3da14abd5..c743753ab 100644 --- a/config/shared/wally-shared.vh +++ b/config/shared/wally-shared.vh @@ -98,7 +98,7 @@ `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) `define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) `define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ // Floating point constants needed for FPU paramerterization @@ -125,7 +125,7 @@ // division constants -`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input +`define DIVN ((((`NF+2)<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input `define LOGR ($clog2(`RADIX)) // r = log(R) `define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc `define LOGRK ($clog2(`RK)) // log2(r*k) From 19096a812adb9e100d98fb1abf1810ab741c77fa Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 May 2023 11:18:27 -0700 Subject: [PATCH 2/5] Added Zifencei ISA to tests where necessary to support new compiler --- setup.sh | 1 + .../riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-uart-timeout-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S | 2 +- 19 files changed, 19 insertions(+), 18 deletions(-) diff --git a/setup.sh b/setup.sh index 2115a0d71..95026beb1 100755 --- a/setup.sh +++ b/setup.sh @@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY} export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin +#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim # Change this for your path to Questa, excluding bin export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin # Path to RISC-V Tools diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S index f04a51d50..b0ad29128 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S @@ -22,7 +22,7 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S index 0bcce74b5..94021491d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S index a71ab485c..f864d255c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S index c728f5721..038b9ce00 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S index 80204cf1c..f48771c5e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S index ceba7374c..0c1c7bbb2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S @@ -36,7 +36,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S index a37e95365..4daddb3fb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S index c18ed2629..101154923 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S index 106580b88..2ed238e23 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" -RVTEST_ISA("RV32I_Zicsr") +RVTEST_ISA("RV32I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout) .equ UART, 0x10000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S index 838e4654d..3aaa58706 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S @@ -22,7 +22,7 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S index 3782ea561..c991721ea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S index 68c77a1aa..80df44a1a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S @@ -22,7 +22,7 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S index bcb93d670..9b8925fb5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S @@ -22,7 +22,7 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S index 0056c9c72..ce15c0525 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S index 68161276c..3f312c9b3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S index e340302e5..a5385e001 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S @@ -35,7 +35,7 @@ #define PLIC_RANGE 0x03FFFFFF #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index e8da53c3a..140c0d97d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -22,7 +22,7 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S index 32423d247..2c2b2ab07 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" -RVTEST_ISA("RV64I_Zicsr") +RVTEST_ISA("RV64I_Zicsr_Zifencei") RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) INIT_TESTS From 7b0d1a78834d76e1e190a420b1c6b55265239055 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 May 2023 11:37:01 -0700 Subject: [PATCH 3/5] Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim --- sim/regression-wally | 4 ++-- testbench/testbench.sv | 4 ++++ testbench/tests.vh | 42 +++++++++++++++++++++++++++++++----------- 3 files changed, 37 insertions(+), 13 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index fa112731a..6e7ccf388 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -85,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( name=test, @@ -132,7 +132,7 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9021b6448..f43b6a429 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -93,6 +93,8 @@ module testbench; "arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64f": if (`F_SUPPORTED) tests = arch64f; "arch64d": if (`D_SUPPORTED) tests = arch64d; + "arch64f_fma": if (`F_SUPPORTED) tests = arch64f_fma; + "arch64d_fma": if (`D_SUPPORTED) tests = arch64d_fma; "arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi; "imperas64i": tests = imperas64i; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; @@ -124,6 +126,8 @@ module testbench; "arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32f": if (`F_SUPPORTED) tests = arch32f; "arch32d": if (`D_SUPPORTED) tests = arch32d; + "arch32f_fma": if (`F_SUPPORTED) tests = arch32f_fma; + "arch32d_fma": if (`D_SUPPORTED) tests = arch32d_fma; "arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi; "imperas32i": tests = imperas32i; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; diff --git a/testbench/tests.vh b/testbench/tests.vh index ffe718188..822705fae 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1066,6 +1066,14 @@ string imperas32f[] = '{ "rv64i_m/I/src/xori-01.S" }; + string arch64f_fma[] = '{ + `RISCVARCHTEST, + //"rv64i_m/F/src/fmadd_b15-01.S", + "rv64i_m/F/src/fmsub_b15-01.S" + // "rv64i_m/F/src/fnmadd_b15-01.S", + // "rv64i_m/F/src/fnmsub_b15-01.S" + }; + string arch64f[] = '{ `RISCVARCHTEST, "rv64i_m/F/src/fdiv_b1-01.S", @@ -1088,8 +1096,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b8-01.S", "rv64i_m/F/src/fsqrt_b9-01.S", - - "rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b11-01.S", @@ -1140,7 +1146,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/flw-align-01.S", "rv64i_m/F/src/fmadd_b1-01.S", "rv64i_m/F/src/fmadd_b14-01.S", - //"rv64i_m/F/src/fmadd_b15-01.S", "rv64i_m/F/src/fmadd_b16-01.S", "rv64i_m/F/src/fmadd_b17-01.S", "rv64i_m/F/src/fmadd_b18-01.S", @@ -1157,7 +1162,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fmin_b19-01.S", "rv64i_m/F/src/fmsub_b1-01.S", "rv64i_m/F/src/fmsub_b14-01.S", - "rv64i_m/F/src/fmsub_b15-01.S", "rv64i_m/F/src/fmsub_b16-01.S", "rv64i_m/F/src/fmsub_b17-01.S", "rv64i_m/F/src/fmsub_b18-01.S", @@ -1188,7 +1192,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fmv.x.w_b29-01.S", "rv64i_m/F/src/fnmadd_b1-01.S", "rv64i_m/F/src/fnmadd_b14-01.S", - // "rv64i_m/F/src/fnmadd_b15-01.S", "rv64i_m/F/src/fnmadd_b16-01.S", "rv64i_m/F/src/fnmadd_b17-01.S", "rv64i_m/F/src/fnmadd_b18-01.S", @@ -1201,7 +1204,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fnmadd_b8-01.S", "rv64i_m/F/src/fnmsub_b1-01.S", "rv64i_m/F/src/fnmsub_b14-01.S", - // "rv64i_m/F/src/fnmsub_b15-01.S", "rv64i_m/F/src/fnmsub_b16-01.S", "rv64i_m/F/src/fnmsub_b17-01.S", "rv64i_m/F/src/fnmsub_b18-01.S", @@ -1238,6 +1240,13 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsw-align-01.S" }; + string arch64d_fma[] = '{ + `RISCVARCHTEST, + //"rv64i_m/D/src/fmadd.d_b15-01.S", + //"rv64i_m/D/src/fmsub.d_b15-01.S", + "rv64i_m/D/src/fnmadd.d_b15-01.S" + // "rv64i_m/D/src/fnmsub.d_b15-01.S" + }; string arch64d[] = '{ `RISCVARCHTEST, @@ -1262,7 +1271,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S", "rv64i_m/D/src/fsqrt.d_b9-01.S", - "rv64i_m/D/src/fadd.d_b10-01.S", "rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b11-01.S", @@ -1526,6 +1534,14 @@ string arch64zbs[] = '{ "rv32i_m/M/src/mulhu-01.S" }; + string arch32f_fma[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fmadd_b15-01.S" + //"rv32i_m/F/src/fmsub_b15-01.S", + // "rv32i_m/F/src/fnmadd_b15-01.S", + // "rv32i_m/F/src/fnmsub_b15-01.S" + }; + string arch32f[] = '{ `RISCVARCHTEST, "rv32i_m/F/src/fdiv_b20-01.S", @@ -1579,7 +1595,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/flw-align-01.S", "rv32i_m/F/src/fmadd_b1-01.S", "rv32i_m/F/src/fmadd_b14-01.S", - "rv32i_m/F/src/fmadd_b15-01.S", "rv32i_m/F/src/fmadd_b16-01.S", "rv32i_m/F/src/fmadd_b17-01.S", "rv32i_m/F/src/fmadd_b18-01.S", @@ -1596,7 +1611,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fmin_b19-01.S", "rv32i_m/F/src/fmsub_b1-01.S", "rv32i_m/F/src/fmsub_b14-01.S", - //"rv32i_m/F/src/fmsub_b15-01.S", "rv32i_m/F/src/fmsub_b16-01.S", "rv32i_m/F/src/fmsub_b17-01.S", "rv32i_m/F/src/fmsub_b18-01.S", @@ -1627,7 +1641,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fmv.x.w_b29-01.S", "rv32i_m/F/src/fnmadd_b1-01.S", "rv32i_m/F/src/fnmadd_b14-01.S", - // "rv32i_m/F/src/fnmadd_b15-01.S", "rv32i_m/F/src/fnmadd_b16-01.S", "rv32i_m/F/src/fnmadd_b17-01.S", "rv32i_m/F/src/fnmadd_b18-01.S", @@ -1640,7 +1653,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fnmadd_b8-01.S", "rv32i_m/F/src/fnmsub_b1-01.S", "rv32i_m/F/src/fnmsub_b14-01.S", - // "rv32i_m/F/src/fnmsub_b15-01.S", "rv32i_m/F/src/fnmsub_b16-01.S", "rv32i_m/F/src/fnmsub_b17-01.S", "rv32i_m/F/src/fnmsub_b18-01.S", @@ -1677,6 +1689,14 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsw-align-01.S" }; + string arch32d_fma[] = '{ + `RISCVARCHTEST, + //"rv32i_m/D/src/fmadd.d_b15-01.S", + //"rv32i_m/D/src/fmsub.d_b15-01.S", + // "rv32i_m/D/src/fnmadd.d_b15-01.S", + "rv32i_m/D/src/fnmsub.d_b15-01.S" + }; + string arch32d[] = '{ `RISCVARCHTEST, "rv32i_m/D/src/fadd.d_b10-01.S", From 02c61a0d25a341639d32b869062f3f48279d730e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 May 2023 13:46:20 -0700 Subject: [PATCH 4/5] Update Coremark makefile --- benchmarks/coremark/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index b412c36ef..7b30dcd3e 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -4,14 +4,14 @@ PORT_DIR = $(CURDIR)/riscv64-baremetal cmbase=../../addins/coremark -work_dir= ../../benchmarks/coremark/work +work_dir= ../benchmarks/coremark/work XLEN ?=64 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \ $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32) -ARCH := rv$(XLEN)im +ARCH := rv$(XLEN)gc PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \ -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \ @@ -23,7 +23,7 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) - cd ../benchmarks/coremark/ +# cd ../benchmarks/coremark/ # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test python3 coremark-postprocess.py @@ -33,7 +33,7 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv extractFunctionRadix.sh $<.elf.objdump $(work_dir)/coremark.bare.riscv: $(sources) Makefile - make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)" + make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)" mkdir -p $(work_dir) mv $(cmbase)/coremark.bare.riscv $(work_dir) From b7ebce148766542c47425eea88ba1fad9bc2dd9b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 May 2023 13:53:03 -0700 Subject: [PATCH 5/5] Fixed division by zero in coremark postprocessing --- benchmarks/coremark/coremark-postprocess.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py index f77f2ef8b..7ad02a09c 100644 --- a/benchmarks/coremark/coremark-postprocess.py +++ b/benchmarks/coremark/coremark-postprocess.py @@ -37,6 +37,14 @@ for lineNum in range(len(logLines)): ICacheAccess = int(contents[-1]) ICacheLineNum = lineNum + 2 +# prevent division by zero +if (dCacheAccess == 0): + dCacheAccess = 1; +if (ICacheAccess == 0): + ICacheAccess = 1; +if (branchesTot == 0): + branchesTot = 1; + # need to add the number of previously added lines to the line number so that they stay in the intedned order. logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n") logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")