diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv
new file mode 100644
index 000000000..77db25e1c
--- /dev/null
+++ b/pipelined/src/lsu/atomic.sv
@@ -0,0 +1,59 @@
+///////////////////////////////////////////
+// atomic.sv
+//
+// Written: Ross Thompson ross1728@gmail.com January 31, 2022
+// Modified:
+//
+// Purpose: atomic data path.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module atomic (
+  input logic                clk,
+  input logic                reset, FlushW, CPUBusy,
+  input logic [`XLEN-1:0]    ReadDataM,
+  input logic [`XLEN-1:0]    WriteDataM, 
+  input logic [`PA_BITS-1:0] LSUPAdrM,
+  input logic [6:0]          LSUFunct7M,
+  input logic [2:0]          LSUFunct3M,
+  input logic [1:0]          LSUAtomicM,
+  input logic [1:0]          PreLSURWM,
+  input logic                IgnoreRequest,
+  input logic                DTLBMissM,
+  output logic [`XLEN-1:0]   FinalAMOWriteDataM,
+  output logic               SquashSCW,
+  output logic [1:0]         LSURWM);
+
+    logic [`XLEN-1:0] AMOResult;
+  logic               MemReadM;
+
+    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
+                  .result(AMOResult));
+    mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
+    assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
+    lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
+        .SquashSCW, .LSURWM);
+
+endmodule  
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 88f28a46a..d980d0a5e 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -93,7 +93,6 @@ module lsu (
 (* mark_debug = "true" *)  logic [`PA_BITS-1:0] 		   PreLSUPAdrM, LocalLSUBusAdr;
   logic [11:0] 				   PreLSUAdrE, LSUAdrE;  
   logic 					   CPUBusy;
-  logic 					   MemReadM;
   logic 					   DCacheStallM;
   logic 					   CacheableM;
   logic 					   SelHPTW;
@@ -301,13 +300,10 @@ module lsu (
   if (`A_SUPPORTED) begin:lrsc
     /*atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .MemRead, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
                     .SquashSCM, .LSURWM, ... ); *** */
-    logic [`XLEN-1:0] AMOResult;
-    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
-                  .result(AMOResult));
-    mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
-    assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
-    lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
-        .SquashSCW, .LSURWM);
+    atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, .LSUFunct7M,
+                  .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .DTLBMissM, 
+                  .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
+
   end else begin:lrsc
     assign SquashSCW = 0;
     assign LSURWM = PreLSURWM;