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synthesis works

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This commit is contained in:
Kevin Kim 2023-08-26 20:20:20 -07:00
parent 7cb3d87554
commit bfba32dfd9
4 changed files with 7 additions and 8 deletions
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2
config/shared/parameter-defs.vh
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@ -3,7 +3,7 @@
`include "BranchPredictorType.vh" `include "BranchPredictorType.vh"
parameter cvw_t P = '{ localparam cvw_t P = '{
FPGA : FPGA, FPGA : FPGA,
XLEN : XLEN, XLEN : XLEN,
IEEE754 : IEEE754, IEEE754 : IEEE754,

0
src/wrappers/drsuwrapper.sv → fpga/src/drsuwrapper.sv
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4
src/wrappers/wallypipelinedcorewrapper.sv
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@ -37,10 +37,10 @@ module wallypipelinedcorewrapper (
input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
// Bus Interface // Bus Interface
input logic [32-1:0] HRDATA, input logic [P.XLEN-1:0] HRDATA,
input logic HREADY, HRESP, input logic HREADY, HRESP,
output logic HCLK, HRESETn, output logic HCLK, HRESETn,
output logic [34-1:0] HADDR, output logic [P.PA_BITS-1:0] HADDR,
output logic [32-1:0] HWDATA, output logic [32-1:0] HWDATA,
output logic [32/8-1:0] HWSTRB, output logic [32/8-1:0] HWSTRB,
output logic HWRITE, output logic HWRITE,

9
synthDC/scripts/synth.tcl
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@ -25,20 +25,19 @@ set maxopt $::env(MAXOPT)
set drive $::env(DRIVE) set drive $::env(DRIVE)
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/config/} eval file copy -force [glob ${cfg}/*.vh] {$outputDir/config/}
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
# Only for FMA class project; comment out when done
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
# Enables name mapping # Enables name mapping
if { $saifpower == 1 } { if { $saifpower == 1 } {
saif_map -start saif_map -start
} }
# Verilog files # Verilog files
#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh]
set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
# Set toplevel # Set toplevel
@ -75,7 +74,7 @@ if { [shell_is_in_topographical_mode] } {
#set alib_library_analysis_path ./$outputDir #set alib_library_analysis_path ./$outputDir
define_design_lib WORK -path ./$outputDir/WORK define_design_lib WORK -path ./$outputDir/WORK
analyze -f sverilog -lib WORK $my_verilog_files analyze -f sverilog -lib WORK $my_verilog_files
elaborate $my_toplevel -parameter P -lib WORK elaborate $my_toplevel -lib WORK
# Set the current_design # Set the current_design
current_design $my_toplevel current_design $my_toplevel