synthesis works

config/shared/parameter-defs.vh

@@ -3,7 +3,7 @@
 
 `include "BranchPredictorType.vh"
 
-parameter cvw_t P = '{ 
+localparam cvw_t P = '{ 
   FPGA :                 FPGA,  
   XLEN :                 XLEN,  
   IEEE754 :              IEEE754, 

src/wrappers/wallypipelinedcorewrapper.sv

@@ -37,10 +37,10 @@ module wallypipelinedcorewrapper (
    input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
    input  logic [63:0]           MTIME_CLINT, 
    // Bus Interface
-   input  logic [32-1:0]     HRDATA,
+   input  logic [P.XLEN-1:0]     HRDATA,
    input  logic                  HREADY, HRESP,
    output logic                  HCLK, HRESETn,
-   output logic [34-1:0]  HADDR,
+   output logic [P.PA_BITS-1:0]  HADDR,
    output logic [32-1:0]     HWDATA,
    output logic [32/8-1:0]   HWSTRB,
    output logic                  HWRITE,

synthDC/scripts/synth.tcl

@@ -25,20 +25,19 @@ set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
 
 eval file copy -force [glob ${cfg}/*.vh] {$outputDir/config/}
+eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
-eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
+#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
-# Only for FMA class project; comment out when done
-# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
-
 # Enables name mapping
 if { $saifpower == 1 } {
     saif_map -start
 }
 
 # Verilog files
+#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh]
 set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel
@@ -75,7 +74,7 @@ if { [shell_is_in_topographical_mode] } {
 #set alib_library_analysis_path ./$outputDir
 define_design_lib WORK -path ./$outputDir/WORK
 analyze -f sverilog -lib WORK $my_verilog_files
-elaborate $my_toplevel -parameter P -lib WORK 
+elaborate $my_toplevel -lib WORK 
 
 # Set the current_design 
 current_design $my_toplevel