From bf9fdcf9f9e8fde26b6a55def1ce11b188004ab9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 27 Jun 2024 04:26:56 -0700 Subject: [PATCH] Cleaned up lint errors in testbench_fp; still not working in Verilator because readvectors receives the wrong unit, fmt, opctrl --- testbench/testbench_fp.sv | 226 +++++++++++++++++++------------------- 1 file changed, 115 insertions(+), 111 deletions(-) diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 7287e6962..5479e0deb 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -66,6 +66,7 @@ module testbench_fp; logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit + logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags logic [4:0] CmpFlg; // Outputed flags logic AnsNaN, ResNaN, NaNGood; @@ -820,13 +821,14 @@ module testbench_fp; end always_comb begin + FpResExtended = {{(P.Q_LEN-P.FLEN){1'b1}}, FpRes}; // select the result to check case (UnitVal) - `FMAUNIT: Res = FpRes; - `DIVUNIT: Res = FpRes; - `CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes}; - `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes; - `CVTFPUNIT: Res = FpRes; + `FMAUNIT: Res = FpResExtended; + `DIVUNIT: Res = FpResExtended; + `CMPUNIT: Res = {{(Q_LEN-XLEN){1'b0}}, CmpRes}; + `CVTINTUNIT: if (WriteIntVal) Res = {{(Q_LEN-XLEN){1'b0}}, IntRes}; else Res = FpResExtended; + `CVTFPUNIT: Res = FpResExtended; endcase // select the flag to check @@ -965,7 +967,7 @@ module testbench_fp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); + assign ResMatch = ((Res[P.FLEN-1:0] === Ans[P.FLEN-1:0]) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign FMAop = (OpCtrlVal == `FMAUNIT); @@ -987,7 +989,7 @@ module testbench_fp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i quad - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1295,25 +1299,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {Int->Fp?, is the integer a long} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> double - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; - Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; - Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b01: begin // double -> long - X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // double -> int - X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1321,25 +1325,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {is the integer a long, is the opperation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; - Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; - Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b01: begin // single -> long - X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // single -> int - X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1347,25 +1351,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {is the integer a long, is the opperation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> half - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; - Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; - Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b01: begin // half -> long - X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // half -> int - X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; end endcase end