diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index 2730a9706..6629af297 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt index 8b6eaf1d8..bcffb1ec5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -294,73 +294,73 @@ deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc BTB_SIZE 16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 # Cache configurations @@ -390,6 +390,10 @@ deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc DCACHE_NUMWAYS 4 ICACHE_NUMWAYS 4 +deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 8 +ICACHE_NUMWAYS 8 + deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc DCACHE_WAYSIZEINBYTES 2048 ICACHE_WAYSIZEINBYTES 2048 @@ -513,3 +517,35 @@ ZFH_SUPPORTED 0 deriv fdqh_rv64gc rv64gc MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 + +# IEEE compatible variants for TestFloat + +deriv f_ieee_rv32gc rv32gc f_rv32gc +IEEE754 1 + +deriv fh_ieee_v32gc rv32gc fh_rv32gc +IEEE754 1 + +deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc +IEEE754 1 + +deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc +IEEE754 1 + +deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc +IEEE754 1 + +deriv f_ieee_rv64gc rv64gc f_rv64gc +IEEE754 1 + +deriv fh_ieee_rv64gc rv64gc fh_rv64gc +IEEE754 1 + +deriv fd_ieee_rv64gc rv64gc fd_rv64gc +IEEE754 1 + +deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc +IEEE754 1 + +deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc +IEEE754 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 60153fdd2..9f0056fad 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -158,7 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index eb021ab0e..8b4b78a4f 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -170,7 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index fe2aa9e51..81b25bc2b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -159,7 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 3714f0749..931725cc4 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 941e11382..3f5c8683a 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index c4e54e346..7f038d87e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -160,7 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3067e9eab..4dd540a9f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/sim/sim-testfloat b/sim/sim-testfloat index 7f22690c0..b7da7104a 100755 --- a/sim/sim-testfloat +++ b/sim/sim-testfloat @@ -9,4 +9,4 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do rv64fpquad $1" +vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 073553e52..96fb0f345 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,4 +10,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do testfloat.do rv64fpquad $1" \ No newline at end of file +vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/testfloat.do b/sim/testfloat.do index f21975389..796b540f3 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -25,7 +25,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 658107f56..5eab7c7ec 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -35,6 +35,8 @@ module testbenchfp; `include "parameter-defs.vh" + parameter MAXVECTORS = 8388610; + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -49,7 +51,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -975,7 +977,7 @@ module testbenchfp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + for(int i=0; i