From bf312bb37c3483dc79d3665a9edc5089c89f09fb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 25 Aug 2021 22:45:13 -0500
Subject: [PATCH] Removed amo logic from ahblite.  Removed many unused signals
 from ahblite.

---
 wally-pipelined/src/ebu/ahblite.sv            | 33 ++-----------------
 wally-pipelined/src/lsu/lsu.sv                |  1 -
 .../src/wally/wallypipelinedhart.sv           |  3 --
 3 files changed, 2 insertions(+), 35 deletions(-)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index b7280a56e..8741baa5f 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -69,9 +69,7 @@ module ahblite (
   // Delayed signals for writes
   output logic [2:0] 	     HADDRD,
   output logic [3:0] 	     HSIZED,
-  output logic 		     HWRITED,
-  // Stalls
-  output logic 		     CommitM
+  output logic 		     HWRITED
 );
 
   logic GrantData;
@@ -141,7 +139,7 @@ module ahblite (
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE);
   // delay write data by one cycle for
-  flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
+  flop #(`XLEN) wdreg(HCLK, DCtoAHBWriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
   // delay signals for subword writes
   flop #(3)   adrreg(HCLK, HADDR[2:0], HADDRD);
   flop #(4)   sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
@@ -154,33 +152,6 @@ module ahblite (
   assign InstrRData = HRDATA;
   assign DCfromAHBReadData = HRDATA;
   assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
-  assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE);
   assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
-  // Carefully decide when to update ReadDataW
-  //   ReadDataMstored holds the most recent memory read.
-  //   We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
-  //   (or else the W stage will accidentally get the M stage's data when the pipeline does advance).
-  assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||
-                        ((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD));
-  flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, HRDATAMasked, CapturedHRDATAMasked);
-
-  always @(posedge HCLK, negedge HRESETn)
-    if (~HRESETn)
-      CapturedDataAvailable <= #1 1'b0;
-    else
-      CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0;
-
-  // *** AMO portion will go away when it is moved into the LSU
-  // Handle AMO instructions if applicable
-  generate
-    if (`A_SUPPORTED) begin
-      logic [`XLEN-1:0] AMOResult;
-      logic [`XLEN-1:0] HRDATAW;
-      amoalu amoalu(.srca(HRDATAW), .srcb(DCtoAHBWriteData), .funct(Funct7M), .width(MemSizeM), 
-                    .result(AMOResult));
-      mux2 #(`XLEN) wdmux(DCtoAHBWriteData, AMOResult, AtomicMaskedM[1], WriteData);
-    end else
-      assign WriteData = DCtoAHBWriteData;
-  endgenerate
 
 endmodule
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 3c17e9f95..ed13ebebe 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -64,7 +64,6 @@ module lsu
    output logic 	       StoreMisalignedFaultM, StoreAccessFaultM,
 
    // connect to ahb
-   input logic 		       CommitM, // should this be generated in the abh interface?
    output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
    output logic 	       DCtoAHBReadM, 
    output logic 	       DCtoAHBWriteM,
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 82a04a9e6..0b1457b90 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -152,8 +152,6 @@ module wallypipelinedhart
   logic [`XLEN-1:0] 	    DCfromAHBReadData;
   logic [`XLEN-1:0] 	    DCtoAHBWriteData;
   
-  logic 		    CommitM;
-  
   logic 		    BPPredWrongE;
   logic 		    BPPredDirWrongM;
   logic 		    BTBPredPCWrongM;
@@ -200,7 +198,6 @@ module wallypipelinedhart
 	  .ReadDataM(ReadDataM),
 
 	  // connected to ahb (all stay the same)
-	  .CommitM(CommitM),
 	  .DCtoAHBPAdrM(DCtoAHBPAdrM),
 	  .DCtoAHBReadM(DCtoAHBReadM),
 	  .DCtoAHBWriteM(DCtoAHBWriteM),