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https://github.com/openhwgroup/cvw
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Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere
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@ -23,8 +23,9 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
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run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF)
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run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF)
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mkdir -p $(WORKING_DIR)/logs
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mkdir -p $(WORKING_DIR)/logs
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time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
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# time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
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echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
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time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST)
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# echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
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obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
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obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
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mkdir -p obj_dir_non_profiling
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mkdir -p obj_dir_non_profiling
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