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Moved a few muxes around after sww changes.

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This commit is contained in:
Ross Thompson 2022-02-16 15:43:03 -06:00
parent 6a2bcfcd01
commit beac362364
3 changed files with 19 additions and 20 deletions
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11
pipelined/src/ifu/ifu.sv
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@ -190,20 +190,25 @@ module ifu (
logic ICacheBusAck; logic ICacheBusAck;
logic save,restore; logic save,restore;
logic [31:0] temp; logic [31:0] temp;
logic SelUncachedAdr;
busdp #(WORDSPERLINE, LINELEN, 32, LOGWPL) busdp #(WORDSPERLINE, LINELEN, LOGWPL)
busdp(.clk, .reset, busdp(.clk, .reset,
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(),
.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBusRead(IFUBusRead), .LSUBusSize(),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(), .LSUBusHWDATA(), .WordCount(),
.DCacheFetchLine(ICacheFetchLine), .DCacheFetchLine(ICacheFetchLine),
.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
.DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF), .DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF),
.FinalWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]), .FinalWriteDataM(), .SelUncachedAdr,
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM()); .BusStall, .BusCommittedM());
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ICacheBusWriteData[32-1:0]),
.s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
if(`IMEM == `MEM_CACHE) begin : icache if(`IMEM == `MEM_CACHE) begin : icache
logic [1:0] IFURWF; logic [1:0] IFURWF;
assign IFURWF = CacheableF ? 2'b10 : 2'b00; assign IFURWF = CacheableF ? 2'b10 : 2'b00;

15
pipelined/src/lsu/busdp.sv
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@ -34,7 +34,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0)
( (
input logic clk, reset, input logic clk, reset,
// bus interface // bus interface
@ -42,7 +42,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
input logic LSUBusAck, input logic LSUBusAck,
output logic LSUBusWrite, output logic LSUBusWrite,
output logic LSUBusRead, output logic LSUBusRead,
output logic [`XLEN-1:0] LSUBusHWDATA,
output logic [2:0] LSUBusSize, output logic [2:0] LSUBusSize,
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
output logic [`PA_BITS-1:0] LSUBusAdr, output logic [`PA_BITS-1:0] LSUBusAdr,
@ -53,12 +52,11 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
input logic DCacheWriteLine, input logic DCacheWriteLine,
output logic DCacheBusAck, output logic DCacheBusAck,
output logic [LINELEN-1:0] DCacheBusWriteData, output logic [LINELEN-1:0] DCacheBusWriteData,
output logic SelUncachedAdr,
// lsu interface // lsu interface
input logic [`PA_BITS-1:0] LSUPAdrM, input logic [`PA_BITS-1:0] LSUPAdrM,
input logic [`XLEN-1:0] FinalWriteDataM, input logic [`XLEN-1:0] FinalWriteDataM,
input logic [WORDLEN-1:0] ReadDataWordM,
output logic [WORDLEN-1:0] ReadDataWordMuxM,
input logic IgnoreRequest, input logic IgnoreRequest,
input logic [1:0] LSURWM, input logic [1:0] LSURWM,
input logic CPUBusy, input logic CPUBusy,
@ -70,26 +68,17 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
localparam integer WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0; localparam integer WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0;
logic [`XLEN-1:0] PreLSUBusHWDATA;
logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [`PA_BITS-1:0] LocalLSUBusAdr;
logic SelUncachedAdr;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
.d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end end
mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
if(LSU == 1) mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
else assign LSUBusHWDATA = '0;
mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
.s(SelUncachedAdr), .y(LSUBusSize)); .s(SelUncachedAdr), .y(LSUBusSize));
mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[WORDLEN-1:0]),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix. busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix.
busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,

13
pipelined/src/lsu/lsu.sv
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@ -194,16 +194,21 @@ module lsu (
logic [`PA_BITS-1:0] WordOffsetAddr; logic [`PA_BITS-1:0] WordOffsetAddr;
logic SelBus; logic SelBus;
logic [LOGWPL-1:0] WordCount; logic [LOGWPL-1:0] WordCount;
logic SelUncachedAdr;
busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp( busdp #(WORDSPERLINE, LINELEN, LOGWPL, 1) busdp(
.clk, .reset, .clk, .reset,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
.WordCount, .LSUBusWriteCrit, .WordCount, .LSUBusWriteCrit,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalWriteDataM, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalWriteDataM,
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM); .BusStall, .BusCommittedM);
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
assign WordOffsetAddr = LSUBusWriteCrit ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; assign WordOffsetAddr = LSUBusWriteCrit ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
if(`DMEM == `MEM_CACHE) begin : dcache if(`DMEM == `MEM_CACHE) begin : dcache
@ -236,7 +241,7 @@ module lsu (
if(`DMEM != `MEM_BUS) begin if(`DMEM != `MEM_BUS) begin
logic [`XLEN-1:0] ReadDataWordMaskedM; logic [`XLEN-1:0] ReadDataWordMaskedM;
assign ReadDataWordMaskedM = CacheableM ? ReadDataWordM : '0; assign ReadDataWordMaskedM = CacheableM ? ReadDataWordM : '0; // AND-gate
subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));