diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 69d79df38..d214ef3b6 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -402,14 +402,6 @@ module testbench;
       // and initialize them to zero (also initilaize them to zero at the start of the next test)
       updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray);
     end
-`ifdef VERILATOR // this macro is defined when verilator is used
-  // Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is 
-  // in the posedge clk block rather than a separate posedge Validate block.  
-  // Until it is fixed, provide a silly posedge Validate block to keep Verilator happy.
-  // https://github.com/verilator/verilator/issues/4967
-  end // restored
-  always @(posedge Validate) // added
-`endif
     if(Validate) begin
       if (PrevPCZero) totalerrors = totalerrors + 1; //  error if PC is stuck at zero
       if (TEST == "buildroot")
@@ -462,10 +454,7 @@ module testbench;
 `endif
       end
     end
-`ifndef VERILATOR
-  // Remove this when issue 4967 is resolved and the posedge Validate logic above is removed
-  end 
-`endif
+  end
 
 
   ////////////////////////////////////////////////////////////////////////////////