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Fix CSR writes from DM

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Matthew 2024-06-14 11:17:41 -05:00
parent 6ae7ac9a6d
commit be7d657f71
3 changed files with 14 additions and 8 deletions
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14
bin/openocd_tcl_wrapper.py
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@ -133,10 +133,16 @@ class OpenOCD:
raise Exception("Error: Hart failed to resume") raise Exception("Error: Hart failed to resume")
def step(self): def step(self):
# Set halt bit #TODO save curent value of dcsr # Set step bit if it isn't already set
self.write_data("DCSR", "0x4") dcsr = int(self.read_data("DCSR"), 16)
# Resume if not (dcsr >> 2) & 0x1:
#self.resume() dcsr |= 0x4
self.write_data("DCSR", hex(dcsr))
# Resume once
self.resume()
# Unset step bit
dcsr &= ~0x4
self.write_data("DCSR", hex(dcsr))
def access_register(self, write, regno, addr_size=None): def access_register(self, write, regno, addr_size=None):
data = 1 << 17 # transfer bit always set data = 1 << 17 # transfer bit always set

6
src/debug/dm.sv
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@ -406,11 +406,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
end end
AC_SCAN : begin AC_SCAN : begin
if ((GPRegNo | FPRegNo) & AcWrite & (Cycle == ScanChainLen)) // Writes to GPR/FPR are shifted in len(GPR) or len(FPR) cycles if (~MiscRegNo & AcWrite & (Cycle == ScanChainLen)) // Writes to CSR/GPR/FPR are shifted in len(CSR/GPR) or len(FPR) cycles
AcState <= AC_UPDATE; AcState <= AC_UPDATE;
else if ((GPRegNo | FPRegNo) & ~AcWrite & (Cycle == P.LLEN)) // Reads from GPR/FPR are shifted in len(ScanReg) cycles else if (~MiscRegNo & ~AcWrite & (Cycle == P.LLEN)) // Reads from CSR/GPR/FPR are shifted in len(ScanReg) cycles
AcState <= AC_IDLE; AcState <= AC_IDLE;
else if (~(GPRegNo | FPRegNo) & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely else if (MiscRegNo & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely
AcState <= AC_IDLE; AcState <= AC_IDLE;
else else
Cycle <= Cycle + 1; Cycle <= Cycle + 1;

2
src/privileged/csr.sv
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@ -329,7 +329,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign InsufficientCSRPrivilegeM = (CSRAdrDM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) | assign InsufficientCSRPrivilegeM = (CSRAdrDM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
(CSRAdrDM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE); (CSRAdrDM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);
assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM &
IllegalCSRSAccessM & IllegalCSRUAccessM /*& IllegalCSRDAccessM*/ | IllegalCSRSAccessM & IllegalCSRUAccessM & IllegalCSRDAccessM |
InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM; InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
// Debug module CSR access // Debug module CSR access