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https://github.com/openhwgroup/cvw
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Merge pull request #114 from ross144/main
Fix the branch predictor's gshare and btb critical path issue
This commit is contained in:
David Harris
GitHub
commit
be5bf22469
@ -247,13 +247,25 @@ if(sys.argv[1] == '-b'):
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currPercent.append(percent)
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dct[PredType] = (currSize, currPercent)
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print(dct)
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fig, axes = plt.subplots()
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marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x'}
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colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue'}
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for cat in dct:
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(x, y) = dct[cat]
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plt.scatter(x, y, label='k')
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plt.plot(x, y)
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plt.ylabel('Prediction Accuracy')
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plt.xlabel('Size (b or k)')
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plt.legend(loc='upper left')
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x=[int(2**int(v)/4) for v in x]
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print(x, y)
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axes.plot(x,y, color=colors[cat])
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axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
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#plt.scatter(x, y, label=cat)
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#plt.plot(x, y)
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#axes.set_xticks([4, 6, 8, 10, 12, 14])
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axes.legend(loc='upper left')
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axes.set_xscale("log")
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axes.set_ylabel('Prediction Accuracy')
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axes.set_xlabel('Size (bytes)')
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axes.set_xticks([16, 64, 256, 1024, 4096, 16384])
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axes.set_xticklabels([16, 64, 256, 1024, 4096, 16384])
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axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
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plt.show()
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@ -33,10 +33,10 @@ module RASPredictor #(parameter int StackSize = 16 )(
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
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input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong
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input logic [3:0] InstrClassD,
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input logic [3:0] InstrClassE, // Instr class
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input logic [3:0] PredInstrClassF,
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input logic WrongBPRetD, // Prediction class is wrong
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input logic RetD,
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input logic RetE, JalE, // Instr class
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input logic BPRetF,
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input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
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output logic [`XLEN-1:0] RASPCF // Top of the stack
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);
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@ -58,17 +58,17 @@ module RASPredictor #(parameter int StackSize = 16 )(
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logic WrongPredRetD;
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assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
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assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
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assign PopF = BPRetF & ~StallD & ~FlushD;
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assign PushE = JalE & ~StallM & ~FlushM;
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assign WrongPredRetD = (WrongPredInstrClassD[2]) & ~StallE & ~FlushE;
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assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); // flushed ret
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assign WrongPredRetD = (WrongBPRetD) & ~StallE & ~FlushE;
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assign FlushedRetDE = (~StallE & FlushE & RetD) | (~StallM & FlushM & RetE); // flushed ret
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assign RepairD = WrongPredRetD | FlushedRetDE ;
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assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~InstrClassD[2]); // Guessed it was a ret, but its not
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assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~RetD); // Guessed it was a ret, but its not
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assign DecRepairD = WrongPredRetD & InstrClassD[2]; // Guessed non ret but is a ret.
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assign DecRepairD = WrongPredRetD & RetD; // Guessed non ret but is a ret.
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assign CounterEn = PopF | PushE | RepairD;
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@ -72,15 +72,12 @@ module bpred (
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logic [1:0] DirPredictionF;
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logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
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logic [`XLEN-1:0] BTAF, RASPCF;
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logic PredictionPCWrongE;
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logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
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logic [3:0] InstrClassD;
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logic [3:0] InstrClassE;
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logic DirPredictionWrongE;
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logic SelBPPredF;
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logic BPPCSrcF;
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logic [`XLEN-1:0] BPPredPCF;
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logic [`XLEN-1:0] PCNext0F;
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logic [`XLEN-1:0] PCCorrectE;
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@ -91,34 +88,45 @@ module bpred (
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logic [`XLEN-1:0] BTAD;
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logic BTBJalF, BTBRetF, BTBJumpF, BTBBranchF;
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logic BPBranchF, BPJumpF, BPRetF, BPJalF;
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logic BPBranchD, BPJumpD, BPRetD, BPJalD;
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logic RetD, JalD;
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logic RetE, JalE;
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logic BranchM, JumpM, RetM, JalM;
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logic BranchW, JumpW, RetW, JalW;
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logic WrongBPRetD;
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logic [`XLEN-1:0] PCW, IEUAdrW;
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// Part 1 branch direction prediction
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// look into the 2 port Sram model. something is wrong.
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if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor
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twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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.BranchE, .BranchM, .PCSrcE);
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end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
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gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .PCW, .DirPredictionF, .DirPredictionWrongE,
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.BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
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.PCSrcE);
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end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
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gshare #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .PCW, .DirPredictionF, .DirPredictionWrongE,
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.BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
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.PCSrcE);
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end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
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gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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.BranchE, .BranchM, .PCSrcE);
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end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
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gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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.BranchE, .BranchM, .PCSrcE);
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end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
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// *** Fix me
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@ -140,18 +148,21 @@ module bpred (
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btb #(`BTB_SIZE)
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TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .PCW,
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.BTAF, .BTAD,
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.BTBPredInstrClassF,
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.BTBPredInstrClassF({BTBJalF, BTBRetF, BTBJumpF, BTBBranchF}),
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.PredictionInstrClassWrongM,
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.IEUAdrE, .IEUAdrM,
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.InstrClassD, .InstrClassE, .InstrClassM);
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.IEUAdrE, .IEUAdrM, .IEUAdrW,
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.InstrClassD({JalD, RetD, JumpD, BranchD}), .InstrClassE({JalE, RetE, JumpE, BranchE}), .InstrClassM({JalM, RetM, JumpM, BranchM}),
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.InstrClassW({JalW, RetW, JumpW, BranchW}));
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// the branch predictor needs a compact decoding of the instruction class.
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if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
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logic [3:0] InstrClassF;
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if (!`INSTR_CLASS_PRED) begin : DirectClassDecode
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// This section is mainly for testing, verification, and PPA comparison.
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// An alternative to using the BTB to store the instruction class is to partially decode
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// the instructions in the Fetch stage into, Jal, Ret, Jump, and Branch instructions.
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// This logic is not described in the text book as of 23 February 2023.
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logic cjal, cj, cjr, cjalr, CJumpF, CBranchF;
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logic JumpF, BranchF;
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logic NCJumpF, NCBranchF;
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if(`C_SUPPORTED) begin
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logic [4:0] CompressedOpcF;
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@ -166,48 +177,44 @@ module bpred (
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assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0;
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end
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assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
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assign BranchF = PostSpillInstrRawF[6:0] == 7'h63;
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assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
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assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
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assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF);
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assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (CJumpF));
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assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5
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(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
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assign BPBranchF = NCBranchF | (`C_SUPPORTED & CBranchF);
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assign BPJumpF = NCJumpF | (`C_SUPPORTED & (CJumpF));
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assign BPRetF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5
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(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
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assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
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assign BPJalF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
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(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
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assign PredInstrClassF = InstrClassF;
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assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
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PredInstrClassF[1];
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end else begin
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assign PredInstrClassF = BTBPredInstrClassF;
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assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
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PredInstrClassF[1];
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// This section connects the BTB's instruction class prediction.
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assign {BPJalF, BPRetF, BPJumpF, BPBranchF} = {BTBJalF, BTBRetF, BTBJumpF, BTBBranchF};
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end
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assign BPPCSrcF = (BPBranchF & DirPredictionF[1]) | BPJumpF;
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// Part 3 RAS
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RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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.PredInstrClassF, .InstrClassD, .InstrClassE,
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.WrongPredInstrClassD, .RASPCF, .PCLinkE);
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.BPRetF, .RetD, .RetE, .JalE,
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.WrongBPRetD, .RASPCF, .PCLinkE);
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assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTAF;
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assign BPPredPCF = BPRetF ? RASPCF : BTAF;
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assign InstrClassD[0] = BranchD;
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assign InstrClassD[1] = JumpD ;
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assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
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assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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assign RetD = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
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assign JalD = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE);
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flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM);
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flopenrc #(2) InstrClassRegE(clk, reset, FlushE, ~StallE, {JalD, RetD}, {JalE, RetE});
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flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, {JalE, RetE, JumpE, BranchE}, {JalM, RetM, JumpM, BranchM});
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flopenrc #(4) InstrClassRegW(clk, reset, FlushM, ~StallW, {JalM, RetM, JumpM, BranchM}, {JalW, RetW, JumpW, BranchW});
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flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
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// branch predictor
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flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, AnyWrongPredInstrClassE, PredictionInstrClassWrongM);
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// pipeline the class
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flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
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flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
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// pipeline the predicted class
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flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, {BPJalF, BPRetF, BPJumpF, BPBranchF}, {BPJalD, BPRetD, BPJumpD, BPBranchD});
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// Check the prediction
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// if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
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@ -218,11 +225,10 @@ module bpred (
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assign PredictionPCWrongE = PCCorrectE != PCD;
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// branch class prediction wrong.
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assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0];
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assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
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assign AnyWrongPredInstrClassD = |({BPJalD, BPRetD, BPJumpD, BPBranchD} ^ {JalD, RetD, JumpD, BranchD});
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assign WrongBPRetD = BPRetD ^ RetD;
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// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
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//assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
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assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
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logic BPPredWrongEAlt;
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@ -232,7 +238,7 @@ module bpred (
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// Output the predicted PC or corrected PC on miss-predict.
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// Selects the BP or PC+2/4.
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mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
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mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, BPPCSrcF, PCNext0F);
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// If the prediction is wrong select the correct address.
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mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);
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// Correct branch/jump target.
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@ -257,10 +263,10 @@ module bpred (
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// could be wrong or the fall through address selected for branch predict not taken.
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// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
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// both without the above inaccuracies.
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assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
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assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (BranchE | JumpE & ~RetE) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & RetE & PCSrcE;
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assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
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assign JumpOrTakenBranchE = (BranchE & PCSrcE) | JumpE;
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flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
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@ -275,5 +281,11 @@ module bpred (
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end else begin
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assign {BTBPredPCWrongM, RASPredPCWrongM, JumpOrTakenBranchM} = '0;
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end
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// **** Fix me
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assign InstrClassM = {JalM, RetM, JumpM, BranchM};
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
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flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
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endmodule
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@ -34,7 +34,7 @@ module btb #(parameter Depth = 10 ) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW,// PC at various stages
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output logic [`XLEN-1:0] BTAF, // BTB's guess at PC
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output logic [`XLEN-1:0] BTAD,
|
||||
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
|
||||
@ -42,14 +42,16 @@ module btb #(parameter Depth = 10 ) (
|
||||
input logic PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
|
||||
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
|
||||
input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
|
||||
input logic [`XLEN-1:0] IEUAdrW,
|
||||
input logic [3:0] InstrClassD, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassE, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassM // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassM, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassW
|
||||
);
|
||||
|
||||
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex;
|
||||
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex;
|
||||
logic [`XLEN-1:0] ResetPC;
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchNextX, MatchXF;
|
||||
logic MatchD, MatchE, MatchM, MatchW, MatchX;
|
||||
logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
|
||||
logic [`XLEN+3:0] TableBTBPredictionF;
|
||||
logic UpdateEn;
|
||||
@ -62,6 +64,7 @@ module btb #(parameter Depth = 10 ) (
|
||||
assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
|
||||
assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
|
||||
assign PCMIndex = {PCM[Depth+1] ^ PCM[1], PCM[Depth:2]};
|
||||
assign PCWIndex = {PCW[Depth+1] ^ PCW[1], PCW[Depth:2]};
|
||||
|
||||
// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
|
||||
// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
|
||||
@ -70,23 +73,18 @@ module btb #(parameter Depth = 10 ) (
|
||||
assign ResetPC = `RESET_VECTOR;
|
||||
assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
|
||||
|
||||
assign MatchF = PCNextFIndex == PCFIndex;
|
||||
assign MatchD = PCNextFIndex == PCDIndex;
|
||||
assign MatchE = PCNextFIndex == PCEIndex;
|
||||
assign MatchM = PCNextFIndex == PCMIndex;
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
assign MatchD = PCFIndex == PCDIndex;
|
||||
assign MatchE = PCFIndex == PCEIndex;
|
||||
assign MatchM = PCFIndex == PCMIndex;
|
||||
assign MatchW = PCFIndex == PCWIndex;
|
||||
assign MatchX = MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, BTAF} :
|
||||
MatchD ? {InstrClassD, BTAD} :
|
||||
MatchE ? {InstrClassE, IEUAdrE} :
|
||||
{InstrClassM, IEUAdrM} ;
|
||||
|
||||
flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
|
||||
|
||||
assign {BTBPredInstrClassF, BTAF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
|
||||
assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BTAD} :
|
||||
MatchE ? {InstrClassE, IEUAdrE} :
|
||||
MatchM ? {InstrClassM, IEUAdrM} :
|
||||
{InstrClassW, IEUAdrW} ;
|
||||
|
||||
assign {BTBPredInstrClassF, BTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredictionF};
|
||||
|
||||
assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
|
||||
|
||||
|
||||
@ -38,17 +38,17 @@ module gshare #(parameter k = 10,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW,
|
||||
input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM;
|
||||
logic MatchNextX, MatchXF;
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchX;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM;
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPredictionF;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM;
|
||||
logic [k-1:0] GHRNextM, GHRNextF;
|
||||
@ -68,22 +68,20 @@ module gshare #(parameter k = 10,
|
||||
assign IndexM = GHRM;
|
||||
end
|
||||
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||
flopenrc #(k) IndexWReg(clk, reset, FlushW, ~StallW, IndexM, IndexW);
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
assign MatchD = BranchD & ~FlushE & (IndexF == IndexD);
|
||||
assign MatchE = BranchE & ~FlushM & (IndexF == IndexE);
|
||||
assign MatchM = BranchM & ~FlushW & (IndexF == IndexM);
|
||||
assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
|
||||
assign MatchX = MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
|
||||
MatchD ? {2{DirPredictionD[1]}} :
|
||||
assign ForwardNewDirPredictionF = MatchD ? {2{DirPredictionD[1]}} :
|
||||
MatchE ? {NewDirPredictionE} :
|
||||
NewDirPredictionM ;
|
||||
MatchM ? {NewDirPredictionM} :
|
||||
NewDirPredictionW ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
assign DirPredictionF = MatchX ? ForwardNewDirPredictionF : TableDirPredictionF;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
@ -91,7 +89,7 @@ module gshare #(parameter k = 10,
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -99,17 +97,18 @@ module gshare #(parameter k = 10,
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewDirPredictionM, NewDirPredictionW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||
|
||||
assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
|
||||
assign GHRF = BranchInstrD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
|
||||
assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
|
||||
assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
|
||||
assign GHRNextF = BPBranchF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
|
||||
assign GHRF = BranchD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
|
||||
assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
|
||||
assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
|
||||
|
||||
assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
|
||||
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNextM, GHRM);
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchM, GHRNextM, GHRM);
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -39,7 +39,7 @@ module gsharebasic #(parameter k = 10,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
input logic BranchE, BranchM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexM;
|
||||
@ -64,7 +64,7 @@ module gsharebasic #(parameter k = 10,
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -73,10 +73,10 @@ module gsharebasic #(parameter k = 10,
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||
|
||||
assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
|
||||
assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||
|
||||
@ -31,12 +31,12 @@
|
||||
module twoBitPredictor #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
input logic BranchInstrE, BranchInstrM,
|
||||
input logic BranchE, BranchM,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
@ -55,18 +55,18 @@ module twoBitPredictor #(parameter k = 10) (
|
||||
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM & ~StallM & ~FlushM),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user