diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 5c8938bca..61855055f 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 1
+`define INSTR_CLASS_PRED 0
 
 module bpred (
   input  logic             clk, reset,
@@ -158,7 +158,7 @@ module bpred (
           .InstrClassM({CallM, ReturnM, JumpM, BranchM}),
           .InstrClassW({CallW, ReturnW, JumpW, BranchW}));
 
-  icpred icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
 		.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
 		.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
 		.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .PredictionInstrClassWrongM, .WrongBPReturnD);
@@ -174,7 +174,6 @@ module bpred (
   // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
   // The next instruction is always valid as no other flush would occur at the same time as the branch and not
   // also flush the branch.  This will change in a superscaler cpu. 
-  assign BPPCWrongE = ;
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
   assign BPWrongE = (PCCorrectE != PCD) & InstrValidE & InstrValidD;
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM);
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 1d6c0ff8d..31c3fed58 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -92,10 +92,14 @@ module btb #(parameter Depth = 10 ) (
   assign {BTBIClassF, BTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF};
 
 
+  logic 				   UpdateEn;
+  
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
-     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
+     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
+
+  assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
 
   flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD);
 
diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv
index 78689806f..f6b0f7d11 100644
--- a/src/ifu/bpred/icpred.sv
+++ b/src/ifu/bpred/icpred.sv
@@ -28,9 +28,8 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 1
 
-module icpred (
+module icpred #(parameter INSTR_CLASS_PRED = 1)(
   input  logic             clk, reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
@@ -49,7 +48,7 @@ module icpred (
   logic 		   AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
   logic 					BPBranchD, BPJumpD, BPReturnD, BPCallD;
 
-  if (!`INSTR_CLASS_PRED) begin : DirectClassDecode
+  if (!INSTR_CLASS_PRED) begin : DirectClassDecode
     // This section is mainly for testing, verification, and PPA comparison.
     // An alternative to using the BTB to store the instruction class is to partially decode
     // the instructions in the Fetch stage into, Call, Return, Jump, and Branch instructions.