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Update div.sv

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Program clean up
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Harshini Srinath 2023-06-12 13:47:09 -07:00 committed by GitHub
parent 15928c5d7b
commit bdd2206817
1 changed files with 25 additions and 25 deletions
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src/mdu/div.sv
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@ -34,7 +34,7 @@ module div import cvw::*; #(parameter cvw_t P) (
input logic IntDivE, // integer division/remainder instruction of any type
input logic DivSignedE, // signed division
input logic W64E, // W-type instructions (divw, divuw, remw, remuw)
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,// Forwarding mux outputs for Source A and B
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
output logic DivBusyE, // Divide is busy - stall pipeline
output logic [P.XLEN-1:0] QuotM, RemM // Quotient and remainder outputs
);