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Almost done with Int division

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cturek 2022-11-22 22:22:59 +00:00
parent 78c2ce5649
commit bdb9e24a66
2 changed files with 15 additions and 17 deletions
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2
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -85,7 +85,7 @@ module fdivsqrt(
.FDivBusyE); .FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc( fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .ForwardedSrcAE,
.MDUE, .n, .ALTB, .m, .BZero, .As, .MDUE, .n, .ALTB, .m, .BZero, .As,
.QmM, .WZero, .DivSM); .QmM, .WZero, .DivSM);
endmodule endmodule

30
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -38,6 +38,7 @@ module fdivsqrtpostproc(
input logic Firstun, input logic Firstun,
input logic SqrtM, input logic SqrtM,
input logic SpecialCaseM, input logic SpecialCaseM,
input logic [`XLEN-1:0] ForwardedSrcAE,
input logic RemOp, MDUE, ALTB, BZero, As, input logic RemOp, MDUE, ALTB, BZero, As,
input logic [`DIVBLEN:0] n, m, input logic [`DIVBLEN:0] n, m,
output logic [`DIVb:0] QmM, output logic [`DIVb:0] QmM,
@ -52,7 +53,7 @@ module fdivsqrtpostproc(
logic [`DIVBLEN:0] NormShift; logic [`DIVBLEN:0] NormShift;
logic [`DIVb:0] IntQuot, NormQuot; logic [`DIVb:0] IntQuot, NormQuot;
logic [`DIVb+3:0] IntRem, NormRem; logic [`DIVb+3:0] IntRem, NormRem;
logic [`DIVb:0] PreResult, Result; logic [`DIVb+3:0] PreResult, Result;
// check for early termination on an exact result. If the result is not exact, the sticky should be set // check for early termination on an exact result. If the result is not exact, the sticky should be set
aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
@ -84,32 +85,31 @@ module fdivsqrtpostproc(
if (NegSticky) begin if (NegSticky) begin
NormQuot = FirstUM; NormQuot = FirstUM;
NormRem = W + RemD; NormRem = W + RemD;
PostInc = 0; PostInc = 0;
end else begin end else begin
NormQuot = FirstU; NormQuot = FirstU;
NormRem = W; NormRem = W;
PostInc = 0; PostInc = 0;
end end
else else
if (NegSticky | weq0) begin if (NegSticky | weq0) begin
NormQuot = FirstU; NormQuot = FirstU;
NormRem = W; NormRem = W;
PostInc = 0; PostInc = 0;
end else begin end else begin
NormQuot = FirstU; NormQuot = FirstU;
NormRem = W - RemD; NormRem = W - RemD;
PostInc = 1; PostInc = 1;
end end
/*
always_comb always_comb
if(ALTB) begin if(ALTB) begin
IntQuot = '0; IntQuot = '0;
IntRem = ForwardedSrcAE; IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
end else if (BZero) begin end else if (BZero) begin
IntQuot = '1; IntQuot = '1;
IntRem = ForwardedSrcAE; IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
end else if (EarlyTerm) begin end else if (WZero) begin
if (weq0) begin if (weq0) begin
IntQuot = FirstU; IntQuot = FirstU;
IntRem = '0; IntRem = '0;
@ -121,22 +121,20 @@ module fdivsqrtpostproc(
IntQuot = NormQuot; IntQuot = NormQuot;
IntRem = NormRem; IntRem = NormRem;
end end
*/
/*
always_comb always_comb
if (RemOp) begin if (RemOp) begin
NormShift = m + (`DIVBLEN)'(`DIVa); NormShift = (m + (`DIVBLEN)'(`DIVa));
PreResult = IntRem; PreResult = IntRem;
end else begin end else begin
NormShift = DIVb - (j << `LOGR); NormShift = ((`DIVBLEN)'(`DIVb) - (n << `LOGR));
PreResult = IntQuot; PreResult = {3'b000, IntQuot};
end end
*/
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
// assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); assign Result = ($signed(PreResult) >>> NormShift) + {{(`DIVb+3){1'b0}}, (PostInc & ~RemOp)};
assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;