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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-07-19 15:13:14 -04:00
commit bdb1ece183
1 changed files with 1 additions and 5 deletions
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6
wally-pipelined/src/cache/dcache.sv vendored
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@ -128,7 +128,6 @@ module dcache
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag; logic [TAGLEN-1:0] VictimTag;
logic ReadDataWEn;
logic AnyCPUReqM; logic AnyCPUReqM;
logic FetchCountFlag; logic FetchCountFlag;
@ -317,11 +316,8 @@ module dcache
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
assign ReadDataWEn = ~StallW |
(CurrState == STATE_MISS_READ_WORD_DELAY);
flopen #(`XLEN) ReadDataWReg(.clk(clk), flopen #(`XLEN) ReadDataWReg(.clk(clk),
.en(ReadDataWEn), .en(~StallW),
.d(FinalReadDataWordM), .d(FinalReadDataWordM),
.q(ReadDataW)); .q(ReadDataW));