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updated pma tests for simpler test lib

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Kip Macsai-Goren 2022-01-05 22:10:12 +00:00
parent 8a8f903342
commit bd977efc7b
5 changed files with 1153 additions and 991 deletions
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3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
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@ -30,7 +30,8 @@
rv32i_sc_tests = \
WALLY-MMU-SV32 \
WALLY-PMP
# WALLY-PMA \
target_tests_nosim = WALLY-PMA \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))

1970
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output
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File diff suppressed because it is too large Load Diff

116
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
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@ -2,7 +2,7 @@
//
// WALLY-PMA
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu> (Copied heavily from SV48 test).
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2021-06-15
//
@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.S"
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
// Ideally this should mean that a test can be written by simply adding .4byte statements as below.
# ---------------------------------------------------------------------------------------------
# Test Contents
@ -31,36 +31,108 @@
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.8byte [x28 Value], [x29 Value], [x30 value]'
# '.4byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.8byte [address], [value], [test type]'
# '.4byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler
#
# ---------------------------------------------------------------------------------------------
# =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
# Tests memory load, store, and /* *** execute? */ permissions based on table 12.3 in the *** riscv book, copied below
# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
# Test 12.3.2.1.1 check enabled devices
# | Region | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
.8byte 0x1000, 0x0, 0xB # | ROM | Any | YES | NO | YES | YES | NO | NO | # *** Impossible to write? how am I supposed to put a known value in ROM to read out?
.8byte 0x2000000, 0x0, 0xB # | CLINT | Any | YES | YES | NO | NO | NO | NO |
.8byte 0xC000000, 0x0, 0xB # | PLIC | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x10000000, 0x0, 0xB # | UART0 | 8-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x20000000, 0x0, 0xB # | GPIO | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x800F0000, 0x0, 0xB # | DRAM | Any | YES | YES | YES | YES | YES | YES |
# *** the dram one has a little offset so we don't accidentally write over the code of this test.
# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO |
# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO |
# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
# Test 12.3.2.1.2 Check Regions with no enabled device fail all
.8byte 0x0000, 0x0, 0xC
.8byte 0x3000, 0x0, 0xC
.8byte 0x4000000, 0x0, 0xC
.8byte 0xE0000000, 0x0, 0xC
.8byte 0x12000000, 0x0, 0xC
.8byte 0xA0000000, 0x0, 0xC
# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
.8byte 0x0, 0x0, 0x3 // terminate tests
# ----------------- ROM ---------------------
# *** the rom is read only and these read tests depend on reading a known value out of memory.
# Is there some guaranteed value that I can read out of the ROM
# otherwise the read test can be modified to just check that the read happened,
# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
# .4byte 0x1000, 0xBEEF0001, 0x0 # 32-bit write: store access fault
# .4byte 0x1000, 0xBEEF0001, 0x1 # 32-bit read: success
# .4byte 0x1000, 0xBEEF0002, 0x12 # 16-bit write: store access fault
# .4byte 0x1000, 0xBEEF0002, 0x15 # 16-bit read: success
# .4byte 0x1000, 0xBEEF0003, 0x13 # 08-bit write: store access fault
# .4byte 0x1000, 0xBEEF0003, 0x16 # 08-bit read: success
# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
# .4byte 0x1000, 0x111, 0x2 # execute: success
# ----------------- CLINT ---------------------
.4byte 0x2000000, 0xBEEF00B5, 0x0 # 32-bit write: success
.4byte 0x2000000, 0xBEEF00B5, 0x1 # 32-bit read: success
.4byte 0x2000000, 0xBEEF00B6, 0x12 # 16-bit write: success
.4byte 0x2000000, 0xBEEF00B6, 0x15 # 16-bit read: success
.4byte 0x2000000, 0xBEEF00B7, 0x13 # 08-bit write: success
.4byte 0x2000000, 0xBEEF00B7, 0x16 # 08-bit read: success
.4byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- PLIC ---------------------
.4byte 0xC000000, 0xBEEF00B9, 0x0 # 32-bit write: success
.4byte 0xC000000, 0xBEEF00B9, 0x1 # 32-bit read: success
.4byte 0xC000000, 0xBEEF00BA, 0x12 # 16-bit write: store access fault
.4byte 0xC000000, 0xBEEF00BA, 0x15 # 16-bit read: load access fault
.4byte 0xC000000, 0xBEEF00BB, 0x13 # 08-bit write: store access fault
.4byte 0xC000000, 0xBEEF00BB, 0x16 # 08-bit read: load access fault
.4byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- UART0 ---------------------
.4byte 0x10000000, 0xBEEF00BD, 0x0 # 32-bit write: store access fault
.4byte 0x10000000, 0xBEEF00BD, 0x1 # 32-bit read: load access fault
.4byte 0x10000000, 0xBEEF00BE, 0x12 # 16-bit write: store access fault
.4byte 0x10000000, 0xBEEF00BE, 0x15 # 16-bit read: load access fault
.4byte 0x10000000, 0xBEEF00BF, 0x13 # 08-bit write: success
.4byte 0x10000000, 0xBEEF00BF, 0x16 # 08-bit read: success
.4byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- GPIO ---------------------
.4byte 0x1012000, 0xBEEF00C1, 0x0 # 32-bit write: success
.4byte 0x1012000, 0xBEEF00C1, 0x1 # 32-bit read: success
.4byte 0x1012000, 0xBEEF00C2, 0x12 # 16-bit write: store access fault
.4byte 0x1012000, 0xBEEF00C2, 0x15 # 16-bit read: load access fault
.4byte 0x1012000, 0xBEEF00C3, 0x13 # 08-bit write: store access fault
.4byte 0x1012000, 0xBEEF00C3, 0x16 # 08-bit read: load access fault
.4byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- DRAM ---------------------
# the following is already tested by the fact that this test runs without error:
# 32 bit reads and writes into DRAM,
# Execution in DRAM
# offset by 0xf000 to avoid overwriting the program
.4byte 0x8000F000, 0xBEEF00C5, 0x12 # 16-bit write: success
.4byte 0x8000F000, 0xBEEF00C5, 0x15 # 16-bit read: success
.4byte 0x8000F000, 0xBEEF00C6, 0x13 # 08-bit write: success
.4byte 0x8000F000, 0xBEEF00C6, 0x16 # 08-bit read: success
# ----------------- Inaccessible ---------------------
# show that load, store, and jalr cause faults in a region not defined by PMAs.
# *** should I go through every possible inaccessible region of memory or is one just fine?
.4byte 0xD000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault
.4byte 0xD000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault
.4byte 0x1000, 0x111, 0x2 # execute: instruction access fault
.4byte 0x0, 0x0, 0x3 // terminate tests

53
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S
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@ -295,9 +295,17 @@ test_loop:
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
li x7, 0x0 # : : :
beq x30, x7, write_test # 0x0 : Write to address : 0xf : None
beq x30, x7, write32_test # 0x0 : Write 32 bits to address : 0xf : None
li x7, 0x12 # : : :
beq x30, x7, write16_test # 0x12 : Write 16 bits to address : 0xf : None
li x7, 0x13 # : : :
beq x30, x7, write08_test # 0x13 : Write 8 bits to address : 0xf : None
li x7, 0x1 # : : :
beq x30, x7, read_test # 0x1 : Read from address : 0xd, 0xbad : readvalue in hex
beq x30, x7, read32_test # 0x1 : Read 32 bits from address : 0xd, 0xbad : readvalue in hex
li x7, 0x15 # : : :
beq x30, x7, read16_test # 0x15 : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x16 # : : :
beq x30, x7, read08_test # 0x16 : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x2 # : : :
beq x30, x7, executable_test # 0x2 : test executable at address : 0xc, 0xbad : leading 12 bits of the li instr written to address. In general this is 0x111. (be sure to also write a return instruction)
li x7, 0x3 # : : :
@ -321,20 +329,49 @@ test_loop:
# ------------------------------------------------------------------------------------------------------------------------------------
j terminate_test # default case: break
write_test:
# address to write in x28, value in x29
write32_test:
# address to write in x28, word value in x29
sw x29, 0(x28)
j test_loop # go to next test case
read_test:
# address to read in x28, expected value in x29 (unused, but there for your perusal).
write16_test:
# address to write in x28, halfword value in x29
sh x29, 0(x28)
j test_loop # go to next test case
write08_test:
# address to write in x28, value in x29
sb x29, 0(x28)
j test_loop # go to next test case
read32_test:
# address to read in x28, expected 32 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lw x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 4
addi x16, x16, 4
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
read16_test:
# address to read in x28, expected 16 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lh x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
read08_test:
# address to read in x28, expected 8 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lb x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
goto_s_mode:
li a0, 3 # Trap handler behavior (go to machine mode)
mv a1, x28 # return VPN

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output
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@ -99,7 +99,7 @@ beef00c4
00000bad
00000000
00000009
deadbeef
00000000
deadbeef
deadbeef
deadbeef