From bd46cf76a922be82b5f86b7634a21039f74816f9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 6 Jul 2022 18:34:30 -0500 Subject: [PATCH] Fixed an issue with direct map cache's nextway logic. Also found a small error in the replacement policy. --- pipelined/src/cache/cache.sv | 3 ++- pipelined/src/cache/cachereplacementpolicy.sv | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 7f5d2de7a..f6aad78e7 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -185,7 +185,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); assign FlushWayFlag = FlushWay[NUMWAYS-1]; - assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; + if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; + else assign NextFlushWay = FlushWay[NUMWAYS-1]; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index cb33480dc..d407bc284 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -59,8 +59,8 @@ module cachereplacementpolicy // Replacement Bits: Register file // Needs to be resettable for simulation, but could omit reset for synthesis *** always_ff @(posedge clk) - if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; - else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD; + if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0; + else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD; assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index;