merged radix-2 sqrt into divider - doesnt work yet

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545

pipelined/src/fpu/otfc.sv

@@ -62,36 +62,31 @@ endmodule
 // Square Root OTFC, Radix 2 //
 ///////////////////////////////
 module sotfc2(
-  input  logic         clk,
+  input  logic         sp, sz,
-  input  logic         Start,
+  input  logic [`DIVb-1:0] C,
-  input  logic         sp, sn,
+  input logic [`DIVb:0] S, SM,
-  input  logic         Sqrt,
+  output logic [`DIVb:0] SNext, SMNext
-  input  logic [`DIVLEN+3:0] C,
-  output logic [`DIVLEN-2:0] Sq,
-  output logic [`DIVLEN+3:0] S, SM
 );
   //  The on-the-fly converter transfers the square root 
   //  bits to the quotient as they come.
   //  Use this otfc for division and square root.
-  logic [`DIVLEN+3:0] SNext, SMNext, SMux;
+  logic [`DIVb:0] CExt;
 
-  flopr #(`DIVLEN+4) SMreg(clk, Start, SMNext, SM);
+  assign CExt = {1'b1, C};
-  mux2 #(`DIVLEN+4) Smux(SNext, {3'b000, Sqrt, {(`DIVLEN){1'b0}}}, Start, SMux);
-  flop #(`DIVLEN+4) Sreg(clk, SMux, S);
 
   always_comb begin
     if (sp) begin
-      SNext  = S | (C & ~(C << 1));
+      SNext  = S | (CExt & ~(CExt << 1));
       SMNext = S;
-    end else if (sn) begin
+    end else if (sz) begin
-      SNext  = SM | (C & ~(C << 1));
-      SMNext = SM;
-    end else begin        // If sp and sn are not true, then sz is
       SNext  = S;
-      SMNext = SM | (C & ~(C << 1));
+      SMNext = SM | (CExt & ~(CExt << 1));
+    end else begin        // If sp and sz are not true, then sn is
+      SNext  = SM | (CExt & ~(CExt << 1));
+      SMNext = SM;
     end 
   end
-  assign Sq = S[`DIVLEN] ? S[`DIVLEN-1:1] : S[`DIVLEN-2:0];
+
 endmodule
 
 module otfc4 (

pipelined/src/fpu/qsel.sv

@@ -66,25 +66,29 @@ endmodule
 // Adder Input Generation, Radix 2 //
 ////////////////////////////////////
 module fgen2 (
-  input  logic sp, sn,
+  input  logic sp, sz,
-  input  logic [`DIVLEN+3:0] C, S, SM,
+  input  logic [`DIVb-1:0] C,
-  output logic [`DIVLEN+3:0] F
+  input  logic [`DIVb:0] S, SM,
+  output logic [`DIVb+3:0] F
 );
-  logic [`DIVLEN+3:0] FP, FN, FZ;
+  logic [`DIVb+3:0] FP, FN, FZ;
+  logic [`DIVb+3:0] SExt, SMExt, CExt;
+
+  assign SExt = {3'b0, S};
+  assign SMExt = {3'b0, SM};
+  assign CExt = {4'hf, C};
 
   // Generate for both positive and negative bits
-  assign FP = ~(S << 1) & C;
+  assign FP = ~(SExt << 1) & CExt;
-  assign FN = (SM << 1) | (C & (~C << 2));
+  assign FN = (SMExt << 1) | (CExt & (~CExt << 2));
   assign FZ = '0;
 
   // Choose which adder input will be used
 
   always_comb
     if (sp)       F = FP;
-    else if (sn)  F = FN;
+    else if (sz)  F = FZ;
-    else          F = FZ;
+    else          F = FN;
-
-  // assign F = sp ? FP : (sn ? FN : FZ);
 
 endmodule
 

pipelined/src/fpu/srt.sv

@@ -72,6 +72,7 @@ module srt(
   logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVb+3:0]  DBar, D2, DBar2; // Q4.N-1
   logic [`DIVb:0] QMMux;
+  logic [`DIVb-1:0] NextC;
   logic [`DIVb-1:0] CMux;
   logic [`DIVb:0] SMux;
 
@@ -86,11 +87,22 @@ module srt(
   if (`RADIX == 2) begin : nextw
     assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
     assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
+    assign NextC   = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
   end else begin
     assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
     assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
+    assign NextC   = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
   end
 
+
+//   mux2   #(`DIVb+4) wsmux(NextWSN, {{3{Sqrt}}, X}, DivStart, WSN); //*** modified for sqrt which doesnt work
+//   flopen   #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
+//   mux2   #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
+//   flopen   #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
+//   flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
+//   mux2 #(`DIVb) Cmux(NextC, {Sqrt, {(`DIVb-1){1'b0}}}, DivStart, CMux);
+//   flop #(`DIVb) cflop(clk, CMux, C[0]);
+
   mux2   #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
   flopen   #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
   mux2   #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
@@ -132,6 +144,7 @@ module srt(
     end
   endgenerate
 
+
   // if starting a new divison set Q to 0 and QM to -1
   mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
   flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
@@ -196,6 +209,7 @@ module divinteration (
 	// 0001 = -2
   if(`RADIX == 2) begin : qsel
     qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz);
+    fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F);
   end else begin
     qsel4 qsel4(.D, .WS, .WC, .Sqrt, .q);
     // fgen4 fgen4(.s(q), .C, .S, .SM, .F);
@@ -218,13 +232,14 @@ module divinteration (
   //  WSA, WCA = WS + WC - qD
   assign AddIn = Sqrt ? F : Dsel;
   if (`RADIX == 2) begin : csa
-    csa #(`DIVb+4) csa(WS, WC, AddIn, qp, WSA, WCA);
+    csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~Sqrt, WSA, WCA);
   end else begin
     csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~Sqrt, WSA, WCA);
   end
 
   if (`RADIX == 2) begin : otfc
     otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
+    sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext);
   end else begin
     otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
     // sotfc4 sotfc4(.s(q), .Sqrt, .C, .S, .SM, .SNext, .SMNext);
@@ -254,3 +269,7 @@ module csa #(parameter N=69) (
   assign out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) | 
 		    (in2[N-2:0] & in3[N-2:0]), cin};
 endmodule
+
+
+
+