diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 8067ba412..49828ab38 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -40,28 +40,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, output logic [3:0] m_axi_wstrb, output logic m_axi_wlast, output logic m_axi_wvalid, - input logic m_axi_wready, - // axi 4 write response channel - input logic [3:0] m_axi_bid, - input logic [1:0] m_axi_bresp, - input logic m_axi_bvalid, - output logic m_axi_bready, - // axi 4 read address channel - output logic [3:0] m_axi_arid, - output logic [12:0] m_axi_araddr, - output logic [7:0] m_axi_arlen, - output logic [2:0] m_axi_arsize, - output logic [1:0] m_axi_arburst, - output logic [3:0] m_axi_arcache, - output logic m_axi_arvalid, - input logic m_axi_arready, - // axi 4 read data channel - input logic [3:0] m_axi_rid, - input logic [31:0] m_axi_rdata, - input logic [1:0] m_axi_rresp, - input logic m_axi_rlast, - input logic m_axi_rvalid, - output logic m_axi_rready + input logic m_axi_wready ); localparam TotalFrameLengthBits = 2*48+32+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); @@ -133,10 +112,5 @@ module packetizer import cvw::*; #(parameter cvw_t P, assign m_axi_wlast = BurstDone; assign m_axi_wvalid = (CurrState == STATE_TRANS); - assign m_axi_bready = 1'b1; // *** probably wrong. - - // we aren't using the read channels. This ethernet device isn't going to read anything for now - assign {m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arcache, m_axi_arvalid, m_axi_rready} = '0; - endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 2bcabbfa4..5bc47b1ba 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -597,10 +597,6 @@ module testbench; rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi); - // a bunch of these signals would be needed for the xilinx ethernet IP - // but I switched to using https://github.com/alexforencich/verilog-ethernet - // so most arn't needed anymore. *** remove once I've confirmed this - // works in synthesis. logic m_axi_awready; // axi 4 write data channel logic [31:0] m_axi_wdata; @@ -608,27 +604,6 @@ module testbench; logic m_axi_wlast; logic m_axi_wvalid; logic m_axi_wready; - // axi 4 write response channel - logic [3:0] m_axi_bid; - logic [1:0] m_axi_bresp; - logic m_axi_bvalid; - logic m_axi_bready; - // axi 4 read address channel - logic [3:0] m_axi_arid; - logic [12:0] m_axi_araddr; - logic [7:0] m_axi_arlen; - logic [2:0] m_axi_arsize; - logic [1:0] m_axi_arburst; - logic [3:0] m_axi_arcache; - logic m_axi_arvalid; - logic m_axi_arready; - // axi 4 read data channel - logic [3:0] m_axi_rid; - logic [31:0] m_axi_rdata; - logic [1:0] m_axi_rresp; - logic m_axi_rlast; - logic m_axi_rvalid; - logic m_axi_rready; logic [3:0] mii_txd; logic mii_tx_en, mii_tx_er; @@ -637,10 +612,7 @@ module testbench; logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, - .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready, .m_axi_bid, - .m_axi_bresp, .m_axi_bvalid, .m_axi_bready, .m_axi_arid, .m_axi_araddr, .m_axi_arlen, .m_axi_arsize, - .m_axi_arburst, .m_axi_arcache, .m_axi_arvalid, .m_axi_arready, .m_axi_rid, .m_axi_rdata, .m_axi_rresp, - .m_axi_rlast, .m_axi_rvalid, .m_axi_rready); + .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready); eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), .tx_axis_tdata(m_axi_wdata), .tx_axis_tkeep(m_axi_wstrb), .tx_axis_tvalid(m_axi_wvalid), .tx_axis_tready(m_axi_wready),