From 1c3c8be1488d2f0d9628bc1e1b0654ed33463808 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 22 Mar 2023 17:10:32 +0000 Subject: [PATCH 01/54] support linux --- sim/imperas.ic | 35 +- sim/run-imperas-linux.sh | 9 + sim/wally-imperas-cov.do | 2 +- sim/wally-imperas-no-idv.do | 2 +- sim/wally-imperas.do | 2 +- sim/wally-linux-imperas.do | 150 ++++ src/privileged/csrsr.sv | 2 + testbench/common/wallyTracer.sv | 199 ++++- testbench/testbench-linux-imperas.sv | 1033 ++++++++++++++++++++++++++ 9 files changed, 1398 insertions(+), 36 deletions(-) create mode 100755 sim/run-imperas-linux.sh create mode 100644 sim/wally-linux-imperas.do create mode 100644 testbench/testbench-linux-imperas.sv diff --git a/sim/imperas.ic b/sim/imperas.ic index 3744a4266..82aedf1c9 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,5 +1,7 @@ -#--showoverrides -#--showcommands +#--mpdconsole refRoot +#--gdbconsole +--showoverrides +--showcommands # Core settings --override cpu/unaligned=F @@ -9,7 +11,14 @@ --override cpu/misa_Extensions_mask=0x0 # THIS NEEDS FIXING to 16 ---override cpu/PMP_registers=0 +--override cpu/PMP_registers=16 +--override cpu/PMP_undefined=T + +# Illegal instruction should not contain the bit pattern +# illegal pmp read contained this +# --override cpu/tval_ii_code=F + +--registerset cpu/SCOUNTEREN=0x1 # PMA Settings # 'r': read access allowed @@ -24,16 +33,16 @@ # '8': 8-byte accesses allowed # '-', space: ignored (use for input string formatting). # -# SV39 Memory 0x0000000000 0x7FFFFFFFFF +# SVxx Memory 0x0000000000 0x7FFFFFFFFF # ---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- "; # INITIAL ---callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 "; # BOOTROM ---callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 "; # SDC ---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 "; # CLINT ---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- "; # PLIC ---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- "; # UART0 error - 0x10000000 - 0x100000FF ---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- "; # GPIO error - 0x10006000 - 0x100060FF ---callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 "; # UNCORE_RAM +--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL +--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM +--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC +--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT +--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC +--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF +--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10006000 - 0x100060FF +--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM # Enable the Imperas instruction coverage #-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 @@ -42,7 +51,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh new file mode 100755 index 000000000..5a21b0ebe --- /dev/null +++ b/sim/run-imperas-linux.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +export RISCV=/scratch/moore/RISCV + +export IMPERAS_TOOLS=$(pwd)/imperas.ic +export OTHERFLAGS="+TRACE2LOG_ENABLE=1" +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" + +vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do index dc9e28db7..567ef6b1d 100644 --- a/sim/wally-imperas-cov.do +++ b/sim/wally-imperas-cov.do @@ -51,7 +51,7 @@ vlog +incdir+../config/$1 \ -suppress 7063 \ +acc vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \ -do "coverage save -onexit ./riscv.ucdb" diff --git a/sim/wally-imperas-no-idv.do b/sim/wally-imperas-no-idv.do index 5f300250c..6050211bf 100644 --- a/sim/wally-imperas-no-idv.do +++ b/sim/wally-imperas-no-idv.do @@ -34,7 +34,7 @@ vlog +incdir+../config/$1 \ -suppress 2583 \ -suppress 7063 vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave #-- display input and output signals as hexidecimal values diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 2de97be20..14634c612 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -45,7 +45,7 @@ vlog +incdir+../config/$1 \ -suppress 7063 vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 \ +eval vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do new file mode 100644 index 000000000..a95dc51a3 --- /dev/null +++ b/sim/wally-linux-imperas.do @@ -0,0 +1,150 @@ +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 + + #-- Run the Simulation + #run -all + add log -recursive /* + do linux-wave.do + run -all + + exec ./slack-notifier/slack-notifier.py + +} elseif {$2 eq "buildroot-no-trace"} { + vlog -lint -work work_${1}_${2} \ + +define+USE_IMPERAS_DV \ + +incdir+../config/$1 \ + +incdir+../config/shared \ + +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + ../testbench/testbench-linux-imperas.sv \ + ../testbench/common/*.sv ../src/*/*.sv \ + ../src/*/*/*.sv -suppress 2583 + + # + # start and run simulation + # for profiling add + # vopt -fprofile + # vsim -fprofile+perf + # visualizer -fprofile+perf+dir=fprofile + # + eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \ + -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt + eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \ + -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ + $env(OTHERFLAGS) + + #-- Run the Simulation + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + echo "Don't forget to change DEBUG_LEVEL = 0." + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + #run 100 ns + #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa + #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 + run 14000 ms + #add log -recursive /* + #do linux-wave.do + #run -all + + exec ./slack-notifier/slack-notifier.py + +} elseif {$2 eq "fpga"} { + echo "hello" + vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 + vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt + vsim workopt +nowarn3829 -fatal 7 + + do fpga-wave.do + add log -r /* + run 20 ms + +} else { + if {$2 eq "ahb"} { + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + } else { + # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 + } + vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt + + vsim workopt +nowarn3829 -fatal 7 + + view wave + #-- display input and output signals as hexidecimal values + #do ./wave-dos/peripheral-waves.do + add log -recursive /* + do wave.do + #do wave-bus.do + + # power add generates the logging necessary for saif generation. + #power add -r /dut/core/* + #-- Run the Simulation + + run -all + #power off -r /dut/core/* + #power report -all -bsaif power.saif + noview ../testbench/testbench.sv + view wave +} + + + +#elseif {$2 eq "buildroot-no-trace""} { +# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation +# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt +# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + + #-- Run the Simulation +# run 100 ns +# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa +# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 +# add log -recursive /* +# do linux-wave.do +# run -all + +# exec ./slack-notifier/slack-notifier.py +#} diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index a92aca3be..1b8386f4c 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -52,6 +52,8 @@ module csrsr ( logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS_INT, STATUS_MPP_NEXT; logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE; logic nextMBE, nextSBE; + + initial $monitor("QEMU=%0d STATUS_SXL=%0d STATUS_UXL=%0d", `QEMU, STATUS_SXL, STATUS_UXL); // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index bfe5c4b3f..4df1956ad 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -90,6 +90,7 @@ module wallyTracer(rvviTrace rvvi); assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; logic valid; + int csrid; always_comb begin // Since we are detected the CSR change by comparing the old value we need to @@ -116,7 +117,6 @@ module wallyTracer(rvviTrace rvvi); pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56; csrid = 12'h3A0 + i4; - //if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp); CSRArray[csrid] = pmp; end @@ -125,7 +125,6 @@ module wallyTracer(rvviTrace rvvi); pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i]; csrid = 12'h3B0 + i; - //if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp); CSRArray[csrid] = pmp; end @@ -167,7 +166,17 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + end else begin // hold the old value if the pipeline is stalled. + + // PMP CFG 3A0 to 3AF + for(csrid='h3A0; csrid<='h3AF; csrid++) + CSRArray[csrid] = CSRArrayOld[csrid]; + + // PMP ADDR 3B0 to 3EF + for(csrid='h3B0; csrid<='h3EF; csrid++) + CSRArray[csrid] = CSRArrayOld[csrid]; + CSRArray[12'h300] = CSRArrayOld[12'h300]; CSRArray[12'h310] = CSRArrayOld[12'h310]; CSRArray[12'h305] = CSRArrayOld[12'h305]; @@ -209,7 +218,7 @@ module wallyTracer(rvviTrace rvvi); end end - genvar index; + genvar index; assign rf[0] = '0; for(index = 1; index < NUMREGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; @@ -286,27 +295,177 @@ module wallyTracer(rvviTrace rvvi); // record previous csr value. integer index4; always_ff @(posedge clk) begin - for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin -// IMPERAS - //CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0; - CSRArrayOld[index4] = CSRArray[index4]; - end + CSRArrayOld[12'h300] = CSRArray[12'h300]; + CSRArrayOld[12'h310] = CSRArray[12'h310]; + CSRArrayOld[12'h305] = CSRArray[12'h305]; + CSRArrayOld[12'h341] = CSRArray[12'h341]; + CSRArrayOld[12'h306] = CSRArray[12'h306]; + CSRArrayOld[12'h320] = CSRArray[12'h320]; + CSRArrayOld[12'h302] = CSRArray[12'h302]; + CSRArrayOld[12'h303] = CSRArray[12'h303]; + CSRArrayOld[12'h344] = CSRArray[12'h344]; + CSRArrayOld[12'h304] = CSRArray[12'h304]; + CSRArrayOld[12'h301] = CSRArray[12'h301]; + CSRArrayOld[12'hF14] = CSRArray[12'hF14]; + CSRArrayOld[12'h340] = CSRArray[12'h340]; + CSRArrayOld[12'h342] = CSRArray[12'h342]; + CSRArrayOld[12'h343] = CSRArray[12'h343]; + CSRArrayOld[12'hF11] = CSRArray[12'hF11]; + CSRArrayOld[12'hF12] = CSRArray[12'hF12]; + CSRArrayOld[12'hF13] = CSRArray[12'hF13]; + CSRArrayOld[12'hF15] = CSRArray[12'hF15]; + CSRArrayOld[12'h34A] = CSRArray[12'h34A]; + // MCYCLE and MINSTRET + CSRArrayOld[12'hB00] = CSRArray[12'hB00]; + CSRArrayOld[12'hB02] = CSRArray[12'hB02]; + // supervisor CSRs + CSRArrayOld[12'h100] = CSRArray[12'h100]; + CSRArrayOld[12'h104] = CSRArray[12'h104]; + CSRArrayOld[12'h105] = CSRArray[12'h105]; + CSRArrayOld[12'h141] = CSRArray[12'h141]; + CSRArrayOld[12'h106] = CSRArray[12'h106]; + CSRArrayOld[12'h180] = CSRArray[12'h180]; + CSRArrayOld[12'h140] = CSRArray[12'h140]; + CSRArrayOld[12'h143] = CSRArray[12'h143]; + CSRArrayOld[12'h142] = CSRArray[12'h142]; + CSRArrayOld[12'h144] = CSRArray[12'h144]; + // user CSRs + CSRArrayOld[12'h001] = CSRArray[12'h001]; + CSRArrayOld[12'h002] = CSRArray[12'h002]; + CSRArrayOld[12'h003] = CSRArray[12'h003]; + + // PMP CFG 3A0 to 3AF + for(index4='h3A0; index4<='h3AF; index4++) + CSRArrayOld[index4] = CSRArray[index4]; + + // PMP ADDR 3B0 to 3EF + for(index4='h3B0; index4<='h3EF; index4++) + CSRArrayOld[index4] = CSRArray[index4]; end // check for csr value change. - genvar index5; - for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin - // CSR_W should only indicate the change when the Writeback stage is not stalled and valid. - assign #2 CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0; - assign rvvi.csr_wb[0][0][index5] = CSR_W[index5]; - assign rvvi.csr[0][0][index5] = CSRArray[index5]; + assign #2 CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; + assign #2 CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; + assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; + assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; + assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; + assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0; + assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0; + assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0; + assign #2 CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0; + assign #2 CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0; + assign #2 CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0; + assign #2 CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0; + assign #2 CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0; + assign #2 CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0; + assign #2 CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0; + assign #2 CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0; + assign #2 CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0; + assign #2 CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0; + assign #2 CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0; + assign #2 CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0; + assign #2 CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0; + assign #2 CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0; + assign #2 CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0; + assign #2 CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0; + assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0; + assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0; + assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0; + assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0; + assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0; + assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; + assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; + assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; + assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; + assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; + assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; + + assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; + assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; + assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305]; + assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341]; + assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306]; + assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320]; + assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302]; + assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303]; + assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344]; + assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304]; + assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301]; + assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14]; + assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340]; + assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342]; + assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343]; + assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11]; + assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12]; + assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13]; + assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15]; + assign rvvi.csr_wb[0][0][12'h34A] = CSR_W[12'h34A]; + assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00]; + assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02]; + assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100]; + assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104]; + assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105]; + assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141]; + assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106]; + assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180]; + assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140]; + assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143]; + assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142]; + assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144]; + assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; + assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; + assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; + + assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; + assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; + assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305]; + assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341]; + assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306]; + assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320]; + assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302]; + assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303]; + assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344]; + assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304]; + assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301]; + assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14]; + assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340]; + assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342]; + assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343]; + assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11]; + assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12]; + assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13]; + assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15]; + assign rvvi.csr[0][0][12'h34A] = CSRArray[12'h34A]; + assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00]; + assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02]; + assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100]; + assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104]; + assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105]; + assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141]; + assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106]; + assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180]; + assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140]; + assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143]; + assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142]; + assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144]; + assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; + assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; + assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; + + // PMP CFG 3A0 to 3AF + for(index='h3A0; index<='h3AF; index++) begin + assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign rvvi.csr_wb[0][0][index] = CSR_W[index]; + assign rvvi.csr[0][0][index] = CSRArray[index]; end - -// always @rvvi.clk $display("%t @rvvi.clk=%X", $time, rvvi.clk); -// always @rvvi.csr[0][0]['h300] $display("%t rvvi.csr[0][0]['h300]=%X", $time, rvvi.csr[0][0]['h300]); -// always @rvvi.csr_wb[0][0]['h300] $display("%t rvvi.csr_wb[0][0]['h300]=%X", $time, rvvi.csr_wb[0][0]['h300]); -// always @rvvi.valid[0][0] $display("%t rvvi.valid[0][0]=%X", $time, rvvi.valid[0][0]); - + + // PMP ADDR 3B0 to 3EF + for(index='h3B0; index<='h3EF; index++) begin + assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign rvvi.csr_wb[0][0][index] = CSR_W[index]; + assign rvvi.csr[0][0][index] = CSRArray[index]; + end + // *** implementation only cancel? so sc does not clear? assign rvvi.lrsc_cancel[0][0] = '0; diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv new file mode 100644 index 000000000..64f745e49 --- /dev/null +++ b/testbench/testbench-linux-imperas.sv @@ -0,0 +1,1033 @@ +/////////////////////////////////////////// +// testbench-linux.sv +// +// Written: nboorstin@g.hmc.edu 2021 +// Modified: +// +// Purpose: Testbench for Buildroot Linux +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// This is set from the command line script +// `define USE_IMPERAS_DV + +`ifdef USE_IMPERAS_DV + `include "rvvi/imperasDV.svh" +`endif + +`define DEBUG_TRACE 0 +// Debug Levels +// 0: don't check against QEMU +// 1: print disagreements with QEMU, but only halt on PCW disagreements +// 2: halt on any disagreement with QEMU except CSRs +// 3: halt on all disagreements with QEMU +// 4: print memory accesses whenever they happen +// 5: print everything + +module testbench; + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////// CONFIG //////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Recommend setting all of these in 'do' script using -G option + parameter INSTR_LIMIT = 0; // # of instructions at which to stop + parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim + parameter CHECKPOINT = 0; + parameter RISCV_DIR = "/opt/riscv"; + parameter NO_SPOOFING = 0; + + + `ifdef USE_IMPERAS_DV + import rvviPkg::*; + import rvviApiPkg::*; + import idvApiPkg::*; + `endif + + + + + + + + //////////////////////////////////////////////////////////////////////////////////// + //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// + //////////////////////////////////////////////////////////////////////////////////// + // ========== Testbench Core ========== + integer warningCount = 0; + integer errorCount = 0; + integer fault; + string ProgramAddrMapFile, ProgramLabelMapFile; + // ========== Initialization ========== + string testvectorDir; + string linuxImageDir; + integer memFile; + integer readResult; + // ========== Checkpointing ========== + string checkpointDir; + logic [1:0] initPriv; + // ========== Trace parsing & checking ========== + integer garbageInt; + string garbageString; + `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ + integer traceFile``STAGE; \ + integer matchCount``STAGE; \ + string line``STAGE; \ + string token``STAGE; \ + string ExpectedTokens``STAGE [31:0]; \ + integer index``STAGE; \ + integer StartIndex``STAGE, EndIndex``STAGE; \ + integer TokenIndex``STAGE; \ + integer MarkerIndex``STAGE; \ + integer NumCSR``STAGE; \ + logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [31:0] ExpectedInstr``STAGE; \ + string text``STAGE; \ + string MemOp``STAGE; \ + string RegWrite``STAGE; \ + integer ExpectedRegAdr``STAGE; \ + logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + string ExpectedCSRArray``STAGE[10:0]; \ + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? + `DECLARE_TRACE_SCANNER_SIGNALS(E) + `DECLARE_TRACE_SCANNER_SIGNALS(M) + // M-stage expected values + logic checkInstrM; + integer MIPexpected, SIPexpected; + string name; + logic [`AHBW-1:0] readDataExpected; + // W-stage expected values + logic checkInstrW; + logic [`XLEN-1:0] ExpectedPCW; + logic [31:0] ExpectedInstrW; + string textW; + string RegWriteW; + integer ExpectedRegAdrW; + logic [`XLEN-1:0] ExpectedRegValueW; + string MemOpW; + logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; + integer NumCSRW; + string ExpectedCSRArrayW[10:0]; + logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0]; + logic [`XLEN-1:0] ExpectedIntType; + integer NumCSRWIndex; + integer NumCSRPostWIndex; + logic [`XLEN-1:0] InstrCountW; + // ========== Interrupt parsing & spoofing ========== + string interrupt; + string interruptLine; + integer interruptFile; + integer interruptInstrCount; + integer interruptHartVal; + integer interruptAsyncVal; + longint interruptCauseVal; + longint interruptEpcVal; + longint interruptTVal; + string interruptDesc; + integer NextMIPexpected, NextSIPexpected; + integer NextMepcExpected; + logic [`XLEN-1:0] AttemptedInstructionCount; + // ========== Misc Aliases ========== + `define RF dut.core.ieu.dp.regf.rf + `define PC dut.core.ifu.pcreg.q + `define PRIV_BASE dut.core.priv.priv + `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q + `define CSR_BASE `PRIV_BASE.csr + `define MEIP `PRIV_BASE.MExtInt + `define SEIP `PRIV_BASE.SExtInt + `define MTIP `PRIV_BASE.MTimerInt + `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW + `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q + `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q + `define MIE `CSR_BASE.csri.MIE_REGW + `define MIP `CSR_BASE.csri.MIP_REGW_writeable + `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q + `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q + `define MEPC `CSR_BASE.csrm.MEPCreg.q + `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q + `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q + `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q + `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q + `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q + `define MTVEC `CSR_BASE.csrm.MTVECreg.q + `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q + `define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q + `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] + `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW + `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW + `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT + `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT + `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT + `define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT + `define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT + `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT + `define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT + `define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP + `define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP + `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE + `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE + `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE + `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE + `define UART dut.uncore.uncore.uart.uart.u + `define UART_IER `UART.IER + `define UART_LCR `UART.LCR + `define UART_MCR `UART.MCR + `define UART_SCR `UART.SCR + `define UART_IP `UART.INTR + `define PLIC dut.uncore.uncore.plic.plic + `define PLIC_INT_PRIORITY `PLIC.intPriority + `define PLIC_INT_ENABLE `PLIC.intEn + `define PLIC_THRESHOLD `PLIC.intThreshold + `define PCM dut.core.ifu.PCM + // ========== COMMON MACROS ========== + // Needed for initialization and core + `define SCAN_NEW_INTERRUPT \ + begin \ + $fgets(interruptLine, interruptFile); \ + //$display("Time %t, interruptLine %x", $time, interruptLine); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptInstrCount); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptHartVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%d", interruptAsyncVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptCauseVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptEpcVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%x", interruptTVal); \ + $fgets(interruptLine, interruptFile); \ + $sscanf(interruptLine, "%s", interruptDesc); \ + end + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////// Cache Issue /////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + logic probe; + if (NO_SPOOFING) + assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c + & testbench.dut.core.InstrM != 32'h14021273 + & testbench.dut.core.InstrValidM; + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + ////////////////////////////////// HARDWARE /////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Clock and Reset + logic clk, reset_ext; + logic reset; + initial begin reset_ext <= 1; # 22; reset_ext <= 0; end + always begin clk <= 1; # 5; clk <= 0; # 5; end + // Wally Interface + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic HCLK, HRESETn; + logic HREADY; + logic HSELEXT; + logic [`PA_BITS-1:0] HADDR; + logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic [31:0] GPIOPinsIn; + logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; + + // FPGA-specific Stuff + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + + // Hardwire UART, GPIO pins + assign GPIOPinsIn = 0; + assign UARTSin = 1; + + + + `ifdef USE_IMPERAS_DV + + logic DCacheFlushDone, DCacheFlushStart; + + rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); + wallyTracer wallyTracer(rvvi); + + trace2log idv_trace2log(rvvi); +// trace2cov idv_trace2cov(rvvi); + + // enabling of comparison types + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (1), + .CMP_VR (0), + .CMP_CSR (1) + ) idv_trace2api(rvvi); + + initial begin + int iter; + #1; + MAX_ERRS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + end + + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); + + if (!rvviRefInit("")) begin + msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + // User HPMCOUNTER3 - HPMCOUNTER31 + for (iter='hC03; iter<='hC1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx + end + + // Machine MHPMCOUNTER3 - MHPMCOUNTER31 + for (iter='hB03; iter<='hB1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx + end + + // ERROR Temporary as it powers up as 0x1 + void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason + + // cannot predict this register due to latency between + // pending and taken + void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP + void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP + + // Privileges for PMA are set in the imperas.ic + // volatile (IO) regions are defined here + // only real ROM/RAM areas are BOOTROM and UNCORE_RAM + if (`CLINT_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE))); + end + if (`GPIO_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE))); + end + if (`UART_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); + end + if (`PLIC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE))); + end + if (`SDC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE))); + end + + if(`XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + + void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! + + // Load memory + begin + longint x64; + int x32[2]; + longint index; + + $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); + + $display("RVVI Loading bootmem.bin"); + memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); + index = 'h1000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading ram.bin"); + memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); + index = 'h80000000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading Complete"); + + void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address + end + end + + always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt", dut.core.MTimerInt)); + always @(dut.core.MExtInt) void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt)); + always @(dut.core.SExtInt) void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt)); + always @(dut.core.MSwInt) void'(rvvi.net_push("MSWInterrupt", dut.core.MSwInt)); + + final begin + void'(rvviRefShutdown()); + end + + `endif + + + // Wally + wallypipelinedsoc dut(.clk, .reset, .reset_ext, + .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, + .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, + .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .UARTSin, .UARTSout, + .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); + + // W-stage hardware not needed by Wally itself + parameter nop = 'h13; + logic [`XLEN-1:0] PCW; + logic [31:0] InstrW; + logic InstrValidW; + logic [`XLEN-1:0] IEUAdrW, WriteDataW; + logic TrapW; + `define FLUSHW dut.core.FlushW + `define STALLW dut.core.StallW + flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); + flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW); + flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); + flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); + flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); + flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); + + + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + /////////////////////////////// INITIALIZATION //////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // ========== CHECKPOINTING ========== + `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + initial begin \ + #1; \ + if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ + end + + `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + initial begin \ + if (CHECKPOINT!=0) begin \ + force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + while (reset!==1) #1; \ + while (reset!==0) #1; \ + #1; \ + release `SIGNAL; \ + end \ + end + + `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + for (i=ARRAY_MIN; i= 2)) fault = 1; \ + end + + `define checkCSR(CSR) \ + begin \ + if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ + $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ + if(`DEBUG_TRACE >= 3) fault = 1; \ + end \ + end + + // =========== CORE =========== + assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; + always @(negedge clk) begin + `SCAN_NEW_INSTR_FROM_TRACE(E) + `SCAN_NEW_INSTR_FROM_TRACE(M) + end + + // step 1: register expected state into the write back stage. + always @(posedge clk) begin + if (reset) begin + ExpectedPCW <= '0; + ExpectedInstrW <= '0; + textW <= ""; + RegWriteW <= ""; + ExpectedRegAdrW <= '0; + ExpectedRegValueW <= '0; + ExpectedIEUAdrW <= '0; + MemOpW <= ""; + ExpectedMemWriteDataW <= '0; + ExpectedMemReadDataW <= '0; + NumCSRW <= '0; + end else if(~dut.core.StallW) begin + if(dut.core.FlushW) begin + ExpectedPCW <= '0; + ExpectedInstrW <= '0; + textW <= ""; + RegWriteW <= ""; + ExpectedRegAdrW <= '0; + ExpectedRegValueW <= '0; + ExpectedIEUAdrW <= '0; + MemOpW <= ""; + ExpectedMemWriteDataW <= '0; + ExpectedMemReadDataW <= '0; + NumCSRW <= '0; + end else if (dut.core.ieu.c.InstrValidM) begin + ExpectedPCW <= ExpectedPCM; + ExpectedInstrW <= ExpectedInstrM; + textW <= textM; + RegWriteW <= RegWriteM; + ExpectedRegAdrW <= ExpectedRegAdrM; + ExpectedRegValueW <= ExpectedRegValueM; + ExpectedIEUAdrW <= ExpectedIEUAdrM; + MemOpW <= MemOpM; + ExpectedMemWriteDataW <= ExpectedMemWriteDataM; + ExpectedMemReadDataW <= ExpectedMemReadDataM; + NumCSRW <= NumCSRM; + for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin + ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; + ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; + end + end + #1; + // override on special conditions + if(~dut.core.StallW) begin + if(textW.substr(0,5) == "rdtime") begin + //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); + if(!NO_SPOOFING) + release dut.uncore.uncore.clint.clint.MTIME; + end + //if (ExpectedIEUAdrM == 'h10000005) begin + //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); + //release dut.core.ieu.dp.ReadDataM; + //end + end + end + end + + // step2: make all checks in the write back stage. + assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. + always @(negedge clk) begin + #1; // small delay allows interrupt spoofing to happen first + // always check PC, instruction bits + if (checkInstrW) begin + InstrCountW += 1; + // print progress message + if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); + // turn on waves + if (AttemptedInstructionCount == INSTR_WAVEON) $stop; + // end sim + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + fault = 0; + if (`DEBUG_TRACE >= 1) begin + `checkEQ("PCW",PCW,ExpectedPCW) + //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of + // compressed to uncompressed conversion + `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) + #2; // delay 2 ns. + if(`DEBUG_TRACE >= 5) begin + $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); + $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); + end + if (RegWriteW == "GPR") begin + `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) + $sformat(name,"RF[%02d]",ExpectedRegAdrW); + `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) + end + if (MemOpW.substr(0,2) == "Mem") begin + if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); + `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) + if(MemOpW == "MemR" | MemOpW == "MemRW") begin + if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); + `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) + end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin + if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); + `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) + end + end + // check csr + for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin + case(ExpectedCSRArrayW[NumCSRPostWIndex]) + "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) + "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) + "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) + "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) + "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) + "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) + "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) + "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) + "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) + "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) + "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) + "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) + "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) + "mip": begin + `checkCSR(`CSR_BASE.csrm.MIP_REGW) + if(!NO_SPOOFING) begin + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) + force `MEIP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) + force `SEIP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) + force `UART_IP = 0; + if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) + force `MTIP = 0; + end + end + endcase + end + if (fault == 1) begin + errorCount +=1; + $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); + $stop; $stop; + end + end // if (`DEBUG_TRACE >= 1) + end // if (checkInstrW) + end // always @ (negedge clk) + + + // New IP spoofing + logic globalIntsBecomeEnabled; + assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); + logic checkInterruptM; + assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; + + always @(negedge clk) begin + if(checkInterruptM) begin + if((interruptInstrCount+1) == AttemptedInstructionCount) begin + if(!NO_SPOOFING) begin + case (interruptCauseVal) + 11: begin + force `MEIP = 1; + force `UART_IP = 1; + end + 09: begin + force `SEIP = 1; + force `UART_IP = 1; + end + 07: force `MTIP = 1; + default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); + endcase + $display("Forcing interrupt."); + end + `SCAN_NEW_INTERRUPT + if (globalIntsBecomeEnabled) begin + $display("Enabled global interrupts"); + // The idea here is if a CSR instruction causes an interrupt by + // enabling interrupts, that CSR instruction will commit. + end else begin + // Other instructions, however, will get interrupted and not + // commit, so we don't want our W-stage checker to look for them + // and get confused when it doesn't find them. + garbageInt = $fgets(garbageString,traceFileE); + garbageInt = $fgets(garbageString,traceFileM); + AttemptedInstructionCount += 1; + end + end + end + end + + + + + + + + + + + /////////////////////////////////////////////////////////////////////////////// + //////////////////////////////// Extra Features /////////////////////////////// + /////////////////////////////////////////////////////////////////////////////// + // Function Tracking + FunctionName FunctionName(.reset(reset), + .clk(clk), + .ProgramAddrMapFile(ProgramAddrMapFile), + .ProgramLabelMapFile(ProgramLabelMapFile)); + + // Instr Opcode Tracking + // For waveview convenience + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, + dut.core.ifu.InstrRawF[31:0], + dut.core.ifu.InstrD, dut.core.ifu.InstrE, + dut.core.ifu.InstrM, InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // ------------------ + // Address Translator + // ------------------ + /** + * Walk the page table stored in ram according to sv39 logic and translate a + * virtual address to a physical address. + * + * See section 4.3.2 of the RISC-V Privileged specification for a full + * explanation of the below algorithm. + */ + logic SvMode, PTE_R, PTE_X; + logic [`XLEN-1:0] SATP, PTE; + logic [55:0] BaseAdr, PAdr; + logic [8:0] VPN [2:0]; + logic [11:0] Offset; + function logic [`XLEN-1:0] adrTranslator( + input logic [`XLEN-1:0] adrIn); + begin + int i; + // Grab the SATP register from privileged unit + SATP = dut.core.priv.priv.csr.SATP_REGW; + // Split the virtual address into page number segments and offset + VPN[2] = adrIn[38:30]; + VPN[1] = adrIn[29:21]; + VPN[0] = adrIn[20:12]; + Offset = adrIn[11:0]; + // We do not support sv48; only sv39 + SvMode = SATP[63]; + // Only perform translation if translation is on and the processor is not + // in machine mode + if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin + BaseAdr = SATP[43:0] << 12; + for (i = 2; i >= 0; i--) begin + PAdr = BaseAdr + (VPN[i] << 3); + // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift + // by 3 (the PTE size) to get the requested 64-bit PTE. + PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; + PTE_R = PTE[1]; + PTE_X = PTE[3]; + if (PTE_R | PTE_X) begin + // Leaf page found + break; + end else begin + // Go to next level of table + BaseAdr = PTE[53:10] << 12; + end + end + // Determine which parts of the PTE page number to use based on the + // level of the page table we reached. + if (i == 2) begin + // Gigapage + assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; + end else if (i == 1) begin + // Megapage + assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; + end else begin + // Kilopage + assign adrTranslator = {8'b0, PTE[53:10], Offset}; + end + end else begin + // Direct translation if address translation is not on + assign adrTranslator = adrIn; + end + end + endfunction +endmodule From 2956c11dbc744c746648364d07584de1e6e5396c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 10:51:04 -0500 Subject: [PATCH 02/54] Renamed ebu signal. --- src/ebu/ebufsmarb.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 11d3eb2b6..1990e8f5d 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -57,7 +57,7 @@ module ebufsmarb ( logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; logic [3:0] BeatCount; // Position within a burst transfer - logic CntReset; + logic BeatCntReset; logic [3:0] Threshold; // Number of beats derived from HBURST //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -98,13 +98,13 @@ module ebufsmarb ( // Burst mode logic //////////////////////////////////////////////////////////////////////////////////////////////////// - assign CntReset = NextState == IDLE; + assign BeatCntReset = NextState == IDLE; assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. assign BeatCntEn = (NextState == ARBITRATE) & HREADY; - counter #(4) BeatCounter(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, BeatCount); + counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount); // Used to store data from data phase of AHB. - flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD); + flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD); // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. // HBURST[2:1] Beats From a5e569245b841df3516060b0455f6d723d35d68a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 09:01:07 -0700 Subject: [PATCH 03/54] Shifter capitalization --- src/ieu/shifter.sv | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 8dbdf88e4..bdb40022a 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -35,8 +35,8 @@ module shifter ( input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, Offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount logic Sign; // Sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension @@ -45,45 +45,45 @@ module shifter ( if (`XLEN==32) begin // rv32 with rotates always_comb // funnel mux case({Right, Rotate}) - 2'b00: z = {A[31:0], 31'b0}; - 2'b01: z = {A[31:0], A[31:1]}; - 2'b10: z = {{31{Sign}}, A[31:0]}; - 2'b11: z = {A[30:0], A}; + 2'b00: Z = {A[31:0], 31'b0}; + 2'b01: Z = {A[31:0], A[31:1]}; + 2'b10: Z = {{31{Sign}}, A[31:0]}; + 2'b11: Z = {A[30:0], A}; endcase - assign amttrunc = Amt; // shift amount + assign TruncAmt = Amt; // shift amount end else begin // rv64 with rotates // shifter rotate source select mux logic [`XLEN-1:0] RotA; // rotate source mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) - 2'b00: z = {A[63:0],{63'b0}}; - 2'b01: z = {RotA, RotA[63:1]}; - 2'b10: z = {{63{Sign}}, A[63:0]}; - 2'b11: z = {RotA[62:0], RotA}; + 2'b00: Z = {A[63:0],{63'b0}}; + 2'b01: Z = {RotA, RotA[63:1]}; + 2'b10: Z = {{63{Sign}}, A[63:0]}; + 2'b11: Z = {RotA[62:0], RotA}; endcase - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{Sign}}, A[31:0]}; - else z = {A[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount + if (Right) Z = {{31{Sign}}, A[31:0]}; + else Z = {A[31:0], 31'b0}; + assign TruncAmt = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{Sign}}, A[63:0]}; - else z = {A[63:0], {63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + if (Right) Z = {{63{Sign}}, A[63:0]}; + else Z = {A[63:0], {63'b0}}; + assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end // Opposite offset for right shifts - assign Offset = Right ? amttrunc : ~amttrunc; + assign Offset = Right ? TruncAmt : ~TruncAmt; // Funnel operation - assign zshift = z >> Offset; - assign Y = zshift[`XLEN-1:0]; + assign ZShift = Z >> Offset; + assign Y = ZShift[`XLEN-1:0]; endmodule From 3ce82f93c0064c401d226c7c1a1530392ce33959 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 22:12:04 -0700 Subject: [PATCH 04/54] added premilinary boundary ccrossing cases --- .../references/WALLY-pmp-01.reference_output | 8 +++++- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 ++++++++++++------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index ea5a0cb18..031d87970 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040000 # writeback of value written to PMPADDR1 +20040001 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,6 +26,12 @@ 00000000 00000bad 00000000 +00000005 # read test with access fault when access begins in allowed region and ends in protected NA region +00000000 +00000bad +00000000 +00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region +00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index fc3864d38..dcc2a2dc6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,18 +60,19 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | -.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | +.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | +.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -90,7 +91,14 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 +.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 + +# accesses across PMP region boundaries +.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. + +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. + .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access From 3c6b85606896179c6771685354c9c243d55b5392 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:08:39 -0700 Subject: [PATCH 05/54] Added cause_s_soft_from_m_interrupt --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 00e235f35..85b5ab8c4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -162,6 +162,11 @@ cause_s_soft_interrupt: csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. ret +cause_s_soft_from_m_interrupt: + li t3, 0x2 + csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + cause_m_ext_interrupt: // ========== Configure PLIC ========== li a3, 0x40 From f0027aef2365176b10949702a3ead7770ec55e16 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:09:43 -0700 Subject: [PATCH 06/54] replaced inerrupt tests with allowed versions --- .../privilege/references/WALLY-trap-s-01.reference_output | 8 -------- .../rv64i_m/privilege/src/WALLY-stvec-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-01.S | 4 ++-- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index fe559dfb7..cdc883697 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -60,14 +60,6 @@ 00000000 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -0007ec01 # value to indicate successful vectoring on s soft interrupt -00000000 -00000001 # scause value from s soft interrupt -80000000 -00000000 # stval for ssoft interrupt (0x0) -00000000 -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 0007ec03 # value to indicate successful vectoring on m soft interrupt 00000000 00000003 # scause value from m soft interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 4a4bdb768..05ecf515a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes GOTO_M_MODE -jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode +jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode GOTO_U_MODE // Should cause software interrupt to fire off. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 41d9cd072..b44b6440d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -50,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_s_soft_interrupt +jal cause_s_soft_from_m_interrupt jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt @@ -72,7 +72,7 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1 jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index cfe02f3a6..525e79276 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From e949d3dc4bac0e3119d078dc015ab80e92a310d7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:16:57 -0700 Subject: [PATCH 07/54] ported fixes to 32 bit tests --- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ---- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 089aeba9d..5ee52bee5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -29,10 +29,6 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 -0007ec01 # value to indicate successful vectoring on s soft interrupt -80000001 # scause value from s soft interrupt -00000000 # stval for ssoft interrupt (0x0) -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 0007ec03 # value to indicate successful vectoring on m soft interrupt 80000003 # scause value from m soft interrupt 00000000 # stval for msoft interrupt (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 4b1e2afa4..85758b101 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From 60b2d77c289cb24e3619201f17e3e93644e3bd89 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:18:31 -0700 Subject: [PATCH 08/54] added working tests back into regression --- testbench/tests.vh | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 64b5ca59a..93c1d7ea1 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1852,7 +1852,6 @@ string arch64zbs[] = '{ string wally64priv[] = '{ `WALLYTEST, -// "rv64i_m/privilege/src/BUG66", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S", @@ -1863,15 +1862,15 @@ string arch64zbs[] = '{ "rv64i_m/privilege/src/WALLY-mtvec-01.S", "rv64i_m/privilege/src/WALLY-pma-01.S", "rv64i_m/privilege/src/WALLY-pmp-01.S", -// "rv64i_m/privilege/src/WALLY-sie-01.S", + "rv64i_m/privilege/src/WALLY-sie-01.S", "rv64i_m/privilege/src/WALLY-status-mie-01.S", -// "rv64i_m/privilege/src/WALLY-status-sie-01.S", + "rv64i_m/privilege/src/WALLY-status-sie-01.S", "rv64i_m/privilege/src/WALLY-status-tw-01.S", "rv64i_m/privilege/src/WALLY-status-tvm-01.S", "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv64i_m/privilege/src/WALLY-stvec-01.S", -// "rv64i_m/privilege/src/WALLY-trap-01.S", -// "rv64i_m/privilege/src/WALLY-trap-s-01.S", + "rv64i_m/privilege/src/WALLY-stvec-01.S", + "rv64i_m/privilege/src/WALLY-trap-01.S", + "rv64i_m/privilege/src/WALLY-trap-s-01.S", "rv64i_m/privilege/src/WALLY-trap-sret-01.S", "rv64i_m/privilege/src/WALLY-trap-u-01.S", "rv64i_m/privilege/src/WALLY-wfi-01.S", @@ -1951,15 +1950,15 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-mtvec-01.S", "rv32i_m/privilege/src/WALLY-pma-01.S", "rv32i_m/privilege/src/WALLY-pmp-01.S", -// "rv32i_m/privilege/src/WALLY-sie-01.S", + "rv32i_m/privilege/src/WALLY-sie-01.S", "rv32i_m/privilege/src/WALLY-status-mie-01.S", -// "rv32i_m/privilege/src/WALLY-status-sie-01.S", + "rv32i_m/privilege/src/WALLY-status-sie-01.S", "rv32i_m/privilege/src/WALLY-status-tw-01.S", "rv32i_m/privilege/src/WALLY-status-tvm-01.S", "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv32i_m/privilege/src/WALLY-stvec-01.S", -// "rv32i_m/privilege/src/WALLY-trap-01.S", -// "rv32i_m/privilege/src/WALLY-trap-s-01.S", + "rv32i_m/privilege/src/WALLY-stvec-01.S", + "rv32i_m/privilege/src/WALLY-trap-01.S", + "rv32i_m/privilege/src/WALLY-trap-s-01.S", "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", From b856698ce24a25e250064c8901fe61653201108a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 24 Mar 2023 11:27:41 -0700 Subject: [PATCH 09/54] Revert "added premilinary boundary ccrossing cases" This reverts commit 3ce82f93c0064c401d226c7c1a1530392ce33959. --- .../references/WALLY-pmp-01.reference_output | 8 +----- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 +++++++------------ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index 031d87970..ea5a0cb18 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040001 # writeback of value written to PMPADDR1 +20040000 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,12 +26,6 @@ 00000000 00000bad 00000000 -00000005 # read test with access fault when access begins in allowed region and ends in protected NA region -00000000 -00000bad -00000000 -00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region -00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index dcc2a2dc6..fc3864d38 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,19 +60,18 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | -.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | -.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | +.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -91,14 +90,7 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 - -# accesses across PMP region boundaries -.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. - -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. - +.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access From 1ff15c388266acd1a54a6f4cedfd7dbb48b20480 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 15:01:38 -0500 Subject: [PATCH 10/54] Updated EBU to replace tabs with spaces. --- src/ebu/ahbcacheinterface.sv | 12 +++--- src/ebu/ahbinterface.sv | 34 ++++++++-------- src/ebu/buscachefsm.sv | 26 ++++++------ src/ebu/busfsm.sv | 22 +++++------ src/ebu/controllerinputstage.sv | 32 +++++++-------- src/ebu/ebu.sv | 2 - src/ebu/ebufsmarb.sv | 70 ++++++++++++++++----------------- 7 files changed, 96 insertions(+), 102 deletions(-) diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 7278f4f93..b30a15096 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -35,7 +35,7 @@ module ahbcacheinterface #( parameter LINELEN, // Number of bits in cacheline parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface controls input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ @@ -56,7 +56,7 @@ module ahbcacheinterface #( input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus - output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface @@ -76,10 +76,10 @@ module ahbcacheinterface #( logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data - genvar index; + genvar index; // fetch buffer is made of BEATSPERLINE flip-flops for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer @@ -100,7 +100,7 @@ module ahbcacheinterface #( logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; @@ -118,5 +118,5 @@ module ahbcacheinterface #( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, - .HREADY, .HTRANS, .HWRITE, .HBURST); + .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index ff50f54f5..579791032 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -32,29 +32,28 @@ module ahbinterface #( parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - input logic [`XLEN-1:0] HRDATA, // AHB read data - output logic [`XLEN-1:0] HWDATA, // AHB write data - output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + input logic [`XLEN-1:0] HRDATA, // AHB read data + output logic [`XLEN-1:0] HWDATA, // AHB write data + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write - input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word - input logic [`XLEN-1:0] WriteData, // IEU write data for a store - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus ); - logic CaptureEn; - - localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU + logic CaptureEn; + localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer)); @@ -70,4 +69,5 @@ module ahbinterface #( busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); + endmodule diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 2f3e99228..508a49ff2 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -81,15 +81,15 @@ module buscachefsm #( else CurrState <= #1 NextState; always_comb begin - case(CurrState) - ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; - else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; - else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY) NextState = MEM3; - else NextState = DATA_PHASE; - MEM3: if(Stall) NextState = MEM3; - else NextState = ADR_PHASE; + case(CurrState) + ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; + else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; + else NextState = ADR_PHASE; + DATA_PHASE: if(HREADY) NextState = MEM3; + else NextState = DATA_PHASE; + MEM3: if(Stall) NextState = MEM3; + else NextState = ADR_PHASE; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; @@ -98,8 +98,8 @@ module buscachefsm #( else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_WRITEBACK; - default: NextState = ADR_PHASE; - endcase + default: NextState = ADR_PHASE; + endcase end // IEU, LSU, and IFU controls @@ -117,8 +117,8 @@ module buscachefsm #( assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW))) | - //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. - (CurrState == DATA_PHASE) | + //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. + (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_WRITEBACK & ~HREADY); assign BusCommitted = CurrState != ADR_PHASE; diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 019708a3d..de1dd7583 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -57,20 +57,20 @@ module busfsm ( else CurrState <= #1 NextState; always_comb begin - case(CurrState) - ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; - else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY) NextState = MEM3; - else NextState = DATA_PHASE; - MEM3: if(Stall) NextState = MEM3; - else NextState = ADR_PHASE; - default: NextState = ADR_PHASE; - endcase + case(CurrState) + ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; + else NextState = ADR_PHASE; + DATA_PHASE: if(HREADY) NextState = MEM3; + else NextState = DATA_PHASE; + MEM3: if(Stall) NextState = MEM3; + else NextState = ADR_PHASE; + default: NextState = ADR_PHASE; + endcase end assign BusStall = (CurrState == ADR_PHASE & |BusRW) | -// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. - (CurrState == DATA_PHASE); +// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. + (CurrState == DATA_PHASE); assign BusCommitted = CurrState != ADR_PHASE; diff --git a/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv index 681f12bc9..7a6c76bb9 100644 --- a/src/ebu/controllerinputstage.sv +++ b/src/ebu/controllerinputstage.sv @@ -36,26 +36,26 @@ module controllerinputstage #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( - input logic HCLK, - input logic HRESETn, - input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs - input logic Restore, // Restore a saved manager inputs when it is finally granted - input logic Disable, // Supress HREADY to the non-granted manager - output logic Request, // This manager is making a request + input logic HCLK, + input logic HRESETn, + input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs + input logic Restore, // Restore a saved manager inputs when it is finally granted + input logic Disable, // Supress HREADY to the non-granted manager + output logic Request, // This manager is making a request // controller input - input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation - input logic [2:0] HSIZEIn, // Manager input. AHB transaction width - input logic [2:0] HBURSTIn, // Manager input. AHB burst length + input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation + input logic [2:0] HSIZEIn, // Manager input. AHB transaction width + input logic [2:0] HBURSTIn, // Manager input. AHB burst length input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address - output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority + output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority // controller output - output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation - output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width - output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length + output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width + output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address - input logic HREADYIn // Peripherial ready + input logic HREADYIn // Peripherial ready ); logic HWRITESave; diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index d4e87de2a..17ba080fb 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -89,8 +89,6 @@ module ebu ( logic IFUReq; logic LSUReq; - - assign HCLK = clk; assign HRESETn = ~reset; diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 1990e8f5d..ec1a3d674 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -31,34 +31,33 @@ `include "wally-config.vh" module ebufsmarb ( - input logic HCLK, - input logic HRESETn, + input logic HCLK, + input logic HRESETn, input logic [2:0] HBURST, // AHB burst length - input logic HREADY, + input logic HREADY, - input logic LSUReq, - input logic IFUReq, + input logic LSUReq, + input logic IFUReq, + output logic IFUSave, + output logic IFURestore, + output logic IFUDisable, + output logic IFUSelect, + output logic LSUDisable, + output logic LSUSelect); - output logic IFUSave, - output logic IFURestore, - output logic IFUDisable, - output logic IFUSelect, - output logic LSUDisable, - output logic LSUSelect); - - typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; + typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; statetype CurrState, NextState; - logic both; // Both the LSU and IFU request at the same time - logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration - logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst - logic BeatCntEn; - logic [3:0] BeatCount; // Position within a burst transfer - logic BeatCntReset; - logic [3:0] Threshold; // Number of beats derived from HBURST + logic both; // Both the LSU and IFU request at the same time + logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration + logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst + logic BeatCntEn; + logic [3:0] BeatCount; // Position within a burst transfer + logic BeatCntReset; + logic [3:0] Threshold; // Number of beats derived from HBURST //////////////////////////////////////////////////////////////////////////////////////////////////// // Aribtration scheme @@ -70,8 +69,8 @@ module ebufsmarb ( flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); always_comb case (CurrState) - IDLE: if (both) NextState = ARBITRATE; - else NextState = IDLE; + IDLE: if (both) NextState = ARBITRATE; + else NextState = IDLE; ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE; else NextState = ARBITRATE; default: NextState = IDLE; @@ -100,27 +99,24 @@ module ebufsmarb ( assign BeatCntReset = NextState == IDLE; assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. - assign BeatCntEn = (NextState == ARBITRATE) & HREADY; + // Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently. + // LSU has priority. HREADY serves double duty during a burst transaction. It indicates when the + // beat completes and when the transaction finishes. However there is nothing external to + // differentiate them. The EBU counts the HREADY beats so it knows when to switch to the IFU's + // request. + assign BeatCntEn = (NextState == ARBITRATE) & HREADY; counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount); // Used to store data from data phase of AHB. flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD); - // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. - // HBURST[2:1] Beats - // 00 1 - // 01 4 - // 10 8 - // 11 16 + // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1. + // HBURST[2:1] Beats threshold + // 00 1 0 + // 01 4 3 + // 10 8 7 + // 11 16 15 always_comb if (HBURST[2:1] == 2'b00) Threshold = 4'b0000; else Threshold = (2 << HBURST[2:1]) - 1; -/* case(HBURST) - 0: Threshold = 4'b0000; - 3: Threshold = 4'b0011; // INCR4 - 5: Threshold = 4'b0111; // INCR8 - 7: Threshold = 4'b1111; // INCR16 - default: Threshold = 4'b0000; // INCR without end. - endcase - end */ endmodule From 0511c73e2292f6f15ae3130e64d94de6e20e0d1a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 15:15:38 -0500 Subject: [PATCH 11/54] Replaced tabs -> spaces cache. --- src/cache/cache.sv | 22 +++++----- src/cache/cachefsm.sv | 76 +++++++++++++++++------------------ src/cache/cacheway.sv | 14 ++----- src/cache/subcachelineread.sv | 6 +-- src/ebu/buscachefsm.sv | 50 +++++++++++------------ src/ebu/ebu.sv | 37 +++++++++-------- 6 files changed, 98 insertions(+), 107 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 5d4fca7d5..da7f83276 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -98,9 +98,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic CacheEn; logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel; - logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; + logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; - genvar index; + genvar index; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -154,9 +154,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Bus address for fetch, writeback, or flush writeback mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), + .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path @@ -198,11 +198,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .FlushStage, .CacheRW, .CacheAtomic, .Stall, - .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdr, - .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, - .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, - .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, + .FlushStage, .CacheRW, .CacheAtomic, .Stall, + .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, + .CacheMiss, .CacheAccess, .SelAdr, + .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, + .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, + .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .InvalidateCache, .CacheEn, .LRUWriteEn); endmodule diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 1edb0b65a..c51257be7 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) // performance counter outputs output logic CacheMiss, // Cache miss - output logic CacheAccess, // Cache access + output logic CacheAccess, // Cache access // cache internals input logic CacheHit, // Exactly 1 way hits @@ -69,21 +69,21 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic CacheEn // Enable the cache memory arrays. Disable hold read data constant ); - logic resetDelay; - logic AMO, StoreAMO; - logic AnyUpdateHit, AnyHit; - logic AnyMiss; - logic FlushFlag; + logic resetDelay; + logic AMO, StoreAMO; + logic AnyUpdateHit, AnyHit; + logic AnyMiss; + logic FlushFlag; typedef enum logic [3:0]{STATE_READY, // hit states - // miss states - STATE_FETCH, - STATE_WRITEBACK, - STATE_WRITE_LINE, - STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM - // flush cache - STATE_FLUSH, - STATE_FLUSH_WRITEBACK} statetype; + // miss states + STATE_FETCH, + STATE_WRITEBACK, + STATE_WRITE_LINE, + STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM + // flush cache + STATE_FLUSH, + STATE_FLUSH_WRITEBACK} statetype; statetype CurrState, NextState; @@ -111,26 +111,26 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; - else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; - else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; - else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; - STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; - else NextState = STATE_WRITEBACK; + STATE_READY: if(InvalidateCache) NextState = STATE_READY; + else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; + else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; + else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; + else NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else NextState = STATE_FETCH; + STATE_WRITE_LINE: NextState = STATE_READ_HOLD; + STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; + else NextState = STATE_READY; + STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; + else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. - STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; - else if (FlushFlag) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH; - STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH_WRITEBACK; - default: NextState = STATE_READY; + STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; + else if (FlushFlag) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH; + STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; + else if(CacheBusAck) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH_WRITEBACK; + default: NextState = STATE_READY; endcase end @@ -156,14 +156,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_READY & AnyMiss & LineDirty); assign SelFlush = (CurrState == STATE_READY & FlushCache) | - (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); + (CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_WRITEBACK); assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | - (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); + (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); + (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); + (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); // Bus interface controls assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | (CurrState == STATE_FETCH & ~CacheBusAck) | diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index da40ab705..d7cc0792d 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, - OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( + OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) @@ -86,8 +86,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, assign SelNonHit = FlushWayEn | SetValid | SelWriteback; mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); - //assign SelTag = VictimWay | FlushWay; - //assign SelData = HitWay | FlushWayEn | VictimWayEn; mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData); @@ -95,10 +93,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// - // RT: Can we merge these two muxes? This is also shared in cacheLRU. - //mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelData); - //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData); - assign SetValidWay = SetValid & SelData; assign ClearValidWay = ClearValid & SelData; assign SetDirtyWay = SetDirty & SelData; @@ -117,8 +111,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, .addr(CacheSet), .dout(ReadTag), .bwe('1), .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); - - // AND portion of distributed tag multiplexer assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign DirtyWay = SelTag & Dirty & ValidWay; @@ -152,8 +144,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, always_ff @(posedge clk) begin // Valid bit array, if (reset) ValidBits <= #1 '0; if(CacheEn) begin - ValidWay <= #1 ValidBits[CacheSet]; - if(InvalidateCache) ValidBits <= #1 '0; + ValidWay <= #1 ValidBits[CacheSet]; + if(InvalidateCache) ValidBits <= #1 '0; else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay; end end diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 490618070..58d022a71 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -33,8 +33,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address - input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline - output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. + input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline + output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. ); localparam WORDSPERLINE = LINELEN/MUXINTERVAL; @@ -50,7 +50,7 @@ module subcachelineread #(parameter LINELEN, WORDLEN, genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux - assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)]; + assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)]; end // variable input mux diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 508a49ff2..c619c9135 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -35,33 +35,33 @@ module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL // Log2 of BEATSPERLINE )( - input logic HCLK, - input logic HRESETn, + input logic HCLK, + input logic HRESETn, // IEU interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt - - // ahb cache interface locals. - output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA - - // cache interface - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + + // ahb cache interface locals. + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + + // cache interface + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - output logic [2:0] HBURST // AHB burst length + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; @@ -70,11 +70,11 @@ module buscachefsm #( busstatetype CurrState, NextState; logic [AHBWLOGBWPL-1:0] NextBeatCount; - logic FinalBeatCount; - logic [2:0] LocalBurstType; - logic BeatCntEn; - logic BeatCntReset; - logic CacheAccess; + logic FinalBeatCount; + logic [2:0] LocalBurstType; + logic BeatCntEn; + logic BeatCntReset; + logic CacheAccess; always_ff @(posedge HCLK) if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; @@ -144,7 +144,7 @@ module buscachefsm #( // communication to cache assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount); assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | - (CurrState == DATA_PHASE & BusRW[0]) | + (CurrState == DATA_PHASE & BusRW[0]) | (CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_FETCH); diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 17ba080fb..b045c6aaa 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -52,27 +52,26 @@ module ebu ( output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals - output logic HCLK, HRESETn, - input logic HREADY, // AHB peripheral ready - input logic HRESP, // AHB peripheral response. 0: OK 1: Error - output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration - output logic HWRITE, // AHB transaction direction after arbitration - output logic [2:0] HSIZE, // AHB transaction size after arbitration - output logic [2:0] HBURST, // AHB burst length after arbitration - output logic [3:0] HPROT, // AHB protection. Wally does not use - output logic [1:0] HTRANS, // AHB transaction request after arbitration - output logic HMASTLOCK // AHB master lock. Wally does not use + output logic HCLK, HRESETn, + input logic HREADY, // AHB peripheral ready + input logic HRESP, // AHB peripheral response. 0: OK 1: Error + output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic HWRITE, // AHB transaction direction after arbitration + output logic [2:0] HSIZE, // AHB transaction size after arbitration + output logic [2:0] HBURST, // AHB burst length after arbitration + output logic [3:0] HPROT, // AHB protection. Wally does not use + output logic [1:0] HTRANS, // AHB transaction request after arbitration + output logic HMASTLOCK // AHB master lock. Wally does not use ); - logic LSUDisable; - logic LSUSelect; + logic LSUSelect; logic IFUSave; - logic IFURestore; - logic IFUDisable; - logic IFUSelect; + logic IFURestore; + logic IFUDisable; + logic IFUSelect; logic [`PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; @@ -87,7 +86,7 @@ module ebu ( logic LSUHWRITEOut; logic IFUReq; - logic LSUReq; + logic LSUReq; assign HCLK = clk; assign HRESETn = ~reset; @@ -127,7 +126,7 @@ module ebu ( // HRDATA is sent to all controllers at the core level. ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave, - .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); + .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); endmodule From 730f3ac84e2f417ac3b755ccb6a983307ee10e81 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 17:32:25 -0500 Subject: [PATCH 12/54] Fixed all tap/space issue in RTL. --- src/fpu/fctrl.sv | 80 +++--- src/fpu/fcvt.sv | 28 +- src/fpu/fdivsqrt/fdivsqrt.sv | 76 +++--- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 14 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 50 ++-- src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 6 +- src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 22 +- src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 20 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 34 +-- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 42 +-- src/fpu/fma/fmalza.sv | 4 +- src/fpu/fpu.sv | 222 ++++++++-------- src/fpu/fregfile.sv | 6 +- src/fpu/fsgninj.sv | 54 ++-- src/generic/arrs.sv | 8 +- src/generic/clockgater.sv | 10 +- src/generic/mem/ram1p1rwbe.sv | 63 +++-- src/generic/mem/ram1p1rwbe_64x128.sv | 2 +- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/mem/ram1p1rwbe_64x44.sv | 2 +- src/generic/mem/ram2p1r1wbe.sv | 152 ++++++----- src/generic/mem/ram2p1r1wbe_1024x36.sv | 10 +- src/generic/mem/ram2p1r1wbe_1024x68.sv | 8 +- src/generic/mem/ram2p1r1wbe_128x64.sv | 8 +- src/generic/mem/ram2p1r1wbe_512x64.sv | 8 +- src/generic/mem/ram2p1r1wbe_64x32.sv | 8 +- src/generic/mem/rom1p1r.sv | 94 +++---- src/generic/mem/rom1p1r_128x32.sv | 2 +- src/generic/mem/rom1p1r_128x64.sv | 6 +- src/ieu/bmu/bmuctrl.sv | 8 +- src/ieu/controller.sv | 66 ++--- src/ieu/datapath.sv | 4 +- src/ieu/forward.sv | 2 +- src/ieu/ieu.sv | 34 +-- src/ieu/regfile.sv | 2 +- src/ifu/bpred/RASPredictor.sv | 24 +- src/ifu/bpred/bpred.sv | 88 +++--- src/ifu/bpred/btb.sv | 33 ++- src/ifu/bpred/gshare.sv | 38 +-- src/ifu/bpred/gsharebasic.sv | 20 +- src/ifu/bpred/icpred.sv | 12 +- src/ifu/ifu.sv | 196 +++++++------- src/ifu/irom.sv | 14 +- src/ifu/spill.sv | 37 +-- src/lsu/dtim.sv | 12 +- src/lsu/lrsc.sv | 12 +- src/lsu/lsu.sv | 108 ++++---- src/lsu/subwordread.sv | 34 +-- src/mdu/div.sv | 4 +- src/mdu/mdu.sv | 100 +++---- src/mmu/hptw.sv | 354 ++++++++++++------------- src/mmu/tlb/tlb.sv | 6 +- src/privileged/csr.sv | 14 +- src/privileged/csrc.sv | 90 +++---- src/privileged/csri.sv | 10 +- src/privileged/csrm.sv | 42 +-- src/privileged/csrs.sv | 38 +-- src/privileged/csrsr.sv | 2 +- src/privileged/csru.sv | 2 +- src/privileged/privileged.sv | 160 +++++------ src/privileged/trap.sv | 50 ++-- src/uncore/clint_apb.sv | 2 +- src/uncore/plic_apb.sv | 50 ++-- src/uncore/ram_ahb.sv | 45 ++-- src/uncore/uartPC16550D.sv | 146 +++++----- src/uncore/uncore.sv | 106 ++++---- src/wally/wallypipelinedcore.sv | 76 +++--- src/wally/wallypipelinedsoc.sv | 56 ++-- 68 files changed, 1561 insertions(+), 1577 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5700e1b6a..be10e8007 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -31,53 +31,53 @@ module fctrl ( input logic clk, input logic reset, // input control signals - input logic StallE, StallM, StallW, // stall signals - input logic FlushE, FlushM, FlushW, // flush signals - input logic IntDivE, // is inteteger division - input logic [2:0] FRM_REGW, // rounding mode from CSR - input logic [1:0] STATUS_FS, // is FPU enabled? - input logic FDivBusyE, // is the divider busy - // intruction - input logic [31:0] InstrD, // the full instruction - input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision - input logic [6:0] OpD, // bits 6:0 of instruction - input logic [4:0] Rs2D, // bits 24:20 of instruction - input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode - // input mux selections - output logic XEnD, YEnD, ZEnD, // enable inputs - output logic XEnE, YEnE, ZEnE, // enable inputs - // opperation mux selections - output logic FCvtIntE, FCvtIntW, // convert to integer opperation - output logic [2:0] FrmM, // FP rounding mode - output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format - output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component - output logic FpLoadStoreM, // FP load or store instruction - output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit - output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage + input logic StallE, StallM, StallW, // stall signals + input logic FlushE, FlushM, FlushW, // flush signals + input logic IntDivE, // is inteteger division + input logic [2:0] FRM_REGW, // rounding mode from CSR + input logic [1:0] STATUS_FS, // is FPU enabled? + input logic FDivBusyE, // is the divider busy + // intruction + input logic [31:0] InstrD, // the full instruction + input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision + input logic [6:0] OpD, // bits 6:0 of instruction + input logic [4:0] Rs2D, // bits 24:20 of instruction + input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode + // input mux selections + output logic XEnD, YEnD, ZEnD, // enable inputs + output logic XEnE, YEnE, ZEnE, // enable inputs + // opperation mux selections + output logic FCvtIntE, FCvtIntW, // convert to integer opperation + output logic [2:0] FrmM, // FP rounding mode + output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format + output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component + output logic FpLoadStoreM, // FP load or store instruction + output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit + output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage // register control signals - output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable - output logic FWriteIntE, FWriteIntM, // Write to integer register - output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input - output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input + output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable + output logic FWriteIntE, FWriteIntM, // Write to integer register + output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input + output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input // other control signals output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction - output logic FDivStartE, IDivStartE // Start division or squareroot + output logic FDivStartE, IDivStartE // Start division or squareroot ); `define FCTRLW 12 - logic [`FCTRLW-1:0] ControlsD; // control signals - logic FRegWriteD; // FP register write enable - logic FDivStartD; // start division/sqrt - logic FWriteIntD; // integer register write enable - logic [2:0] OpCtrlD; // Select which opperation to do in each component - logic [1:0] PostProcSelD; // select result in the post processing unit - logic [1:0] FResSelD; // Select one of the results that finish in the memory stage - logic [2:0] FrmD, FrmE; // FP rounding mode - logic [`FMTBITS-1:0] FmtD; // FP format - logic [1:0] Fmt; // format - before possible reduction - logic SupportedFmt; // is the format supported - logic FCvtIntD, FCvtIntM; // convert to integer opperation + logic [`FCTRLW-1:0] ControlsD; // control signals + logic FRegWriteD; // FP register write enable + logic FDivStartD; // start division/sqrt + logic FWriteIntD; // integer register write enable + logic [2:0] OpCtrlD; // Select which opperation to do in each component + logic [1:0] PostProcSelD; // select result in the post processing unit + logic [1:0] FResSelD; // Select one of the results that finish in the memory stage + logic [2:0] FrmD, FrmE; // FP rounding mode + logic [`FMTBITS-1:0] FmtD; // FP format + logic [1:0] Fmt; // format - before possible reduction + logic SupportedFmt; // is the format supported + logic FCvtIntD, FCvtIntM; // convert to integer opperation // FPU Instruction Decoder assign Fmt = Funct7D[1:0]; diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 2f121a75a..32ca7542f 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -30,20 +30,20 @@ `include "wally-config.vh" module fcvt ( - input logic Xs, // input's sign - input logic [`NE-1:0] Xe, // input's exponent - input logic [`NF:0] Xm, // input's fraction - input logic [`XLEN-1:0] Int, // integer input - from IEU - input logic [2:0] OpCtrl, // choose which opperation (look below for values) - input logic ToInt, // is fp->int (since it's writting to the integer register) - input logic XZero, // is the input zero - input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) - output logic [`NE:0] Ce, // the calculated expoent - output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by + input logic Xs, // input's sign + input logic [`NE-1:0] Xe, // input's exponent + input logic [`NF:0] Xm, // input's fraction + input logic [`XLEN-1:0] Int, // integer input - from IEU + input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic XZero, // is the input zero + input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) + output logic [`NE:0] Ce, // the calculated expoent + output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by output logic ResSubnormUf,// does the result underflow or is subnormal - output logic Cs, // the result's sign - output logic IntZero, // is the integer zero? - output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) + output logic Cs, // the result's sign + output logic IntZero, // is the integer zero? + output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) ); // OpCtrls: @@ -60,7 +60,7 @@ module fcvt ( logic [`XLEN-1:0] PosInt; // the positive integer input logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [`NE-2:0] NewBias; // the bias of the final result - logic [`NE-1:0] OldExp; // the old exponent + logic [`NE-1:0] OldExp; // the old exponent logic Signed; // is the opperation with a signed integer? logic Int64; // is the integer 64 bits? logic IntToFp; // is the opperation an int->fp conversion? diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index c69618f43..92f64cbdc 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -29,49 +29,49 @@ `include "wally-config.vh" module fdivsqrt( - input logic clk, - input logic reset, + input logic clk, + input logic reset, input logic [`FMTBITS-1:0] FmtE, - input logic XsE, - input logic [`NF:0] XmE, YmE, - input logic [`NE-1:0] XeE, YeE, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic StallM, - input logic FlushE, - input logic SqrtE, SqrtM, - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic [2:0] Funct3E, Funct3M, - input logic IntDivE, W64E, - output logic DivStickyM, - output logic FDivBusyE, IFDivStartE, FDivDoneE, - output logic [`NE+1:0] QeM, - output logic [`DIVb:0] QmM, - output logic [`XLEN-1:0] FIntDivResultM + input logic XsE, + input logic [`NF:0] XmE, YmE, + input logic [`NE-1:0] XeE, YeE, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic StallM, + input logic FlushE, + input logic SqrtE, SqrtM, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic [2:0] Funct3E, Funct3M, + input logic IntDivE, W64E, + output logic DivStickyM, + output logic FDivBusyE, IFDivStartE, FDivDoneE, + output logic [`NE+1:0] QeM, + output logic [`DIVb:0] QmM, + output logic [`XLEN-1:0] FIntDivResultM ); // Floating-point division and square root module, with optional integer division and remainder // Computes X/Y, sqrt(X), A/B, or A%B - logic [`DIVb+3:0] WS, WC; // Partial remainder components - logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend) - logic [`DIVb-1:0] DPreproc, D; // Iterator Divisor - logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values - logic [`DIVb+1:0] FirstC; // Step tracker - logic Firstun; // Quotient selection - logic WZeroE; // Early termination flag - logic SpecialCaseM; // Divide by zero, square root of negative, etc. - logic DivStartE; // Enable signal for flops during stall - - // Integer div/rem signals - logic BZeroM; // Denominator is zero - logic IntDivM; // Integer operation - logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts - logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor - logic [`XLEN-1:0] AM; // Original Numerator for postprocessor - logic ISpecialCaseE; // Integer div/remainder special cases + logic [`DIVb+3:0] WS, WC; // Partial remainder components + logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend) + logic [`DIVb-1:0] DPreproc, D; // Iterator Divisor + logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values + logic [`DIVb+1:0] FirstC; // Step tracker + logic Firstun; // Quotient selection + logic WZeroE; // Early termination flag + logic SpecialCaseM; // Divide by zero, square root of negative, etc. + logic DivStartE; // Enable signal for flops during stall + + // Integer div/rem signals + logic BZeroM; // Denominator is zero + logic IntDivM; // Integer operation + logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts + logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor + logic [`XLEN-1:0] AM; // Original Numerator for postprocessor + logic ISpecialCaseE; // Integer div/remainder special cases fdivsqrtpreproc fdivsqrtpreproc( // Preprocessor .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), @@ -100,4 +100,4 @@ module fdivsqrt( // Int-specific .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, .FIntDivResultM); -endmodule \ No newline at end of file +endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index b09e9f385..7b92f8c83 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -37,7 +37,7 @@ module fdivsqrtpostproc( input logic [`DIVb+1:0] FirstC, input logic SqrtE, input logic Firstun, SqrtM, SpecialCaseM, NegQuotM, - input logic [`XLEN-1:0] AM, + input logic [`XLEN-1:0] AM, input logic RemOpM, ALTBM, BZeroM, AsM, W64M, input logic [`DIVBLEN:0] nM, mM, output logic [`DIVb:0] QmM, @@ -46,11 +46,11 @@ module fdivsqrtpostproc( output logic [`XLEN-1:0] FIntDivResultM ); - logic [`DIVb+3:0] W, Sum, DM; - logic [`DIVb:0] PreQmM; - logic NegStickyM; - logic weq0E, WZeroM; - logic [`XLEN-1:0] IntDivResultM; + logic [`DIVb+3:0] W, Sum, DM; + logic [`DIVb:0] PreQmM; + logic NegStickyM; + logic weq0E, WZeroM; + logic [`XLEN-1:0] IntDivResultM; ////////////////////////// // Execute Stage: Detect early termination for an exact result @@ -134,4 +134,4 @@ module fdivsqrtpostproc( end else assign FIntDivResultM = IntDivResultM[`XLEN-1:0]; end -endmodule \ No newline at end of file +endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index c5485c26f..9a69085fd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -29,35 +29,35 @@ `include "wally-config.vh" module fdivsqrtpreproc ( - input logic clk, - input logic IFDivStartE, - input logic [`NF:0] Xm, Ym, - input logic [`NE-1:0] Xe, Ye, + input logic clk, + input logic IFDivStartE, + input logic [`NF:0] Xm, Ym, + input logic [`NE-1:0] Xe, Ye, input logic [`FMTBITS-1:0] Fmt, - input logic Sqrt, - input logic XZeroE, - input logic [2:0] Funct3E, - output logic [`NE+1:0] QeM, - output logic [`DIVb+3:0] X, - output logic [`DIVb-1:0] DPreproc, + input logic Sqrt, + input logic XZeroE, + input logic [2:0] Funct3E, + output logic [`NE+1:0] QeM, + output logic [`DIVb+3:0] X, + output logic [`DIVb-1:0] DPreproc, // Int-specific - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic IntDivE, W64E, - output logic ISpecialCaseE, - output logic [`DIVBLEN:0] nE, nM, mM, - output logic NegQuotM, ALTBM, IntDivM, W64M, - output logic AsM, BZeroM, - output logic [`XLEN-1:0] AM + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic IntDivE, W64E, + output logic ISpecialCaseE, + output logic [`DIVBLEN:0] nE, nM, mM, + output logic NegQuotM, ALTBM, IntDivM, W64M, + output logic AsM, BZeroM, + output logic [`XLEN-1:0] AM ); - logic [`DIVb-1:0] XPreproc; - logic [`DIVb:0] PreSqrtX; - logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed - logic [`NE+1:0] QeE; // Quotient Exponent (FP only) - logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator - logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs - logic NumerZeroE; // Numerator is zero (X or A) - logic AZeroE, BZeroE; // A or B is Zero for integer division + logic [`DIVb-1:0] XPreproc; + logic [`DIVb:0] PreSqrtX; + logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed + logic [`NE+1:0] QeE; // Quotient Exponent (FP only) + logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator + logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs + logic NumerZeroE; // Numerator is zero (X or A) + logic AZeroE, BZeroE; // A or B is Zero for integer division if (`IDIV_ON_FPU) begin:intpreproc // Int Supported logic signedDiv, NegQuotE; diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index f18b31f1b..fd0a2a469 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -45,11 +45,11 @@ module fdivsqrtqsel2 ( assign g = ps & pc; assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & - (ps[0]^pc[0])); + (ps[0]^pc[0])); assign sign = (ps[3]^pc[3])^ (ps[2] & pc[2] | ((ps[2]^pc[2]) & - (ps[1]&pc[1] | ((ps[1]^pc[1]) & - (ps[0]&pc[0]))))); + (ps[1]&pc[1] | ((ps[1]^pc[1]) & + (ps[0]&pc[0]))))); // Produce digit = +1, 0, or -1 assign up = magnitude & ~sign; diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index 3a8a110f0..7a0db24d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -32,21 +32,21 @@ module fdivsqrtqsel4 ( input logic [2:0] Dmsbs, input logic [4:0] Smsbs, input logic [7:0] WSmsbs, WCmsbs, - input logic Sqrt, j1, + input logic Sqrt, j1, output logic [3:0] udigit ); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] A; + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] A; - assign PreWmsbs = WCmsbs + WSmsbs; - assign Wmsbs = PreWmsbs[7:1]; - // D = 0001.xxx... - // Dmsbs = | | + assign PreWmsbs = WCmsbs + WSmsbs; + assign Wmsbs = PreWmsbs[7:1]; + // D = 0001.xxx... + // Dmsbs = | | // W = xxxx.xxx... - // Wmsbs = | | + // Wmsbs = | | - logic [3:0] USel4[1023:0]; + logic [3:0] USel4[1023:0]; // Prepopulate selection table; this is constant at compile time always_comb begin @@ -109,5 +109,5 @@ module fdivsqrtqsel4 ( end else A = Dmsbs; // Select quotient digit from lookup table based on A and W - assign udigit = USel4[{A,Wmsbs}]; + assign udigit = USel4[{A,Wmsbs}]; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index 882458106..e508a6d7c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -32,19 +32,19 @@ module fdivsqrtqsel4cmp ( input logic [2:0] Dmsbs, input logic [4:0] Smsbs, input logic [7:0] WSmsbs, WCmsbs, - input logic SqrtE, j1, + input logic SqrtE, j1, output logic [3:0] udigit ); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] A; + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] A; - assign PreWmsbs = WCmsbs + WSmsbs; - assign Wmsbs = PreWmsbs[7:1]; - // D = 0001.xxx... - // Dmsbs = | | + assign PreWmsbs = WCmsbs + WSmsbs; + assign Wmsbs = PreWmsbs[7:1]; + // D = 0001.xxx... + // Dmsbs = | | // W = xxxx.xxx... - // Wmsbs = | | + // Wmsbs = | | logic [6:0] mk2, mk1, mk0, mkm1; logic [6:0] mks2[7:0], mks1[7:0]; @@ -87,5 +87,5 @@ module fdivsqrtqsel4cmp ( else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1 else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0 else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1 - else udigit = 4'b0001; // choose -2 + else udigit = 4'b0001; // choose -2 endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 63ab6c059..53c1711cb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -31,32 +31,32 @@ /* verilator lint_off UNOPTFLAT */ module fdivsqrtstage2 ( input logic [`DIVb-1:0] D, - input logic [`DIVb+3:0] DBar, - input logic [`DIVb:0] U, UM, - input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb+3:0] DBar, + input logic [`DIVb:0] U, UM, + input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, - input logic SqrtE, - output logic un, + input logic SqrtE, + output logic un, output logic [`DIVb+1:0] CNext, - output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSNext, WCNext + output logic [`DIVb:0] UNext, UMNext, + output logic [`DIVb+3:0] WSNext, WCNext ); /* verilator lint_on UNOPTFLAT */ - logic [`DIVb+3:0] Dsel; - logic up, uz; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - logic [`DIVb+3:0] WSA, WCA; + logic [`DIVb+3:0] Dsel; + logic up, uz; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + logic [`DIVb+3:0] WSA, WCA; // Qmient Selection logic // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un) // q encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un); // Sqrt F generation. Extend C, U, UM to Q4.k diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index 007dd18bb..ee92d263b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -30,34 +30,34 @@ module fdivsqrtstage4 ( input logic [`DIVb-1:0] D, - input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] U, UM, - input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] U,UM, + input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, - input logic SqrtE, j1, + input logic SqrtE, j1, output logic [`DIVb+1:0] CNext, - output logic un, - output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSNext, WCNext + output logic un, + output logic [`DIVb:0] UNext, UMNext, + output logic [`DIVb+3:0] WSNext, WCNext ); - logic [`DIVb+3:0] Dsel; - logic [3:0] udigit; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - logic [4:0] Smsbs; - logic [2:0] Dmsbs; - logic [7:0] WCmsbs, WSmsbs; - logic CarryIn; - logic [`DIVb+3:0] WSA, WCA; + logic [`DIVb+3:0] Dsel; + logic [3:0] udigit; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + logic [4:0] Smsbs; + logic [2:0] Dmsbs; + logic [7:0] WCmsbs, WSmsbs; + logic CarryIn; + logic [`DIVb+3:0] WSA, WCA; // Digit Selection logic // u encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 assign Smsbs = U[`DIVb:`DIVb-4]; assign Dmsbs = D[`DIVb-1:`DIVb-3]; assign WCmsbs = WC[`DIVb+3:`DIVb-4]; diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 640e4ed80..59fb3fc3e 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -32,12 +32,12 @@ module fmalza #(WIDTH) ( input logic [WIDTH-1:0] A, // addend input logic [2*`NF+1:0] Pm, // product - input logic Cin, // carry in + input logic Cin, // carry in input logic sub, // subtraction output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result ); - logic [WIDTH:0] F; // most significant bit of F indicates leading digit + logic [WIDTH:0] F; // most significant bit of F indicates leading digit logic [WIDTH-1:0] B; // zero-extended product with same size as aligned A logic [WIDTH-1:0] P, G, K; // propagate, generate, kill for each column logic [WIDTH-1:0] Pp1, Gm1, Km1; // propagate shifted right by 1, generate/kill shifted left 1 diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 8ff36fbfc..32bdfc1ca 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -29,40 +29,40 @@ `include "wally-config.vh" module fpu ( - input logic clk, - input logic reset, + input logic clk, + input logic reset, // Hazards - input logic StallE, StallM, StallW, // stall signals (from HZU) - input logic FlushE, FlushM, FlushW, // flush signals (from HZU) - output logic FPUStallD, // Stall the decode stage (To HZU) - output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) - // CSRs - input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) - input logic [2:0] FRM_REGW, // Rounding mode (from CSR) - // Decode stage - input logic [31:0] InstrD, // instruction (from IFU) - // Execute stage - input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations - input logic IntDivE, W64E, // Integer division on FPU - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU) - input logic [4:0] RdE, // which FP register to write to (from IEU) - output logic FWriteIntE, // integer register write enable (to IEU) - output logic FCvtIntE, // Convert to int (to IEU) - // Memory stage - input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations - input logic [4:0] RdM, // which FP register to write to (from IEU) - output logic FRegWriteM, // FP register write enable (to privileged unit) - output logic FpLoadStoreM, // Fp load instruction? (to LSU) - output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) - output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) - output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU) - output logic [4:0] SetFflagsM, // FPU flags (to privileged unit) - // Writeback stage - input logic [4:0] RdW, // which FP register to write to (from IEU) - input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) - output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) - output logic FCvtIntW, // select FCvtIntRes (to IEU) - output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) + input logic StallE, StallM, StallW, // stall signals (from HZU) + input logic FlushE, FlushM, FlushW, // flush signals (from HZU) + output logic FPUStallD, // Stall the decode stage (To HZU) + output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) + // CSRs + input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) + input logic [2:0] FRM_REGW, // Rounding mode (from CSR) + // Decode stage + input logic [31:0] InstrD, // instruction (from IFU) + // Execute stage + input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations + input logic IntDivE, W64E, // Integer division on FPU + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU) + input logic [4:0] RdE, // which FP register to write to (from IEU) + output logic FWriteIntE, // integer register write enable (to IEU) + output logic FCvtIntE, // Convert to int (to IEU) + // Memory stage + input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations + input logic [4:0] RdM, // which FP register to write to (from IEU) + output logic FRegWriteM, // FP register write enable (to privileged unit) + output logic FpLoadStoreM, // Fp load instruction? (to LSU) + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) + output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) + output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU) + output logic [4:0] SetFflagsM, // FPU flags (to privileged unit) + // Writeback stage + input logic [4:0] RdW, // which FP register to write to (from IEU) + input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) + output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) + output logic FCvtIntW, // select FCvtIntRes (to IEU) + output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) ); // RISC-V FPU specifics: @@ -70,97 +70,97 @@ module fpu ( // - RISC-V detects underflow after rounding // control signals - logic FRegWriteW; // FP register write enable - logic [2:0] FrmM; // FP rounding mode - logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double - logic FDivStartE, IDivStartE; // Start division or squareroot - logic FWriteIntM; // Write to integer register - logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals - logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component - logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage - logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit - logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input - logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input - logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation - logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation - logic FRegWriteE; // Write floating-point register + logic FRegWriteW; // FP register write enable + logic [2:0] FrmM; // FP rounding mode + logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double + logic FDivStartE, IDivStartE; // Start division or squareroot + logic FWriteIntM; // Write to integer register + logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals + logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component + logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage + logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit + logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input + logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input + logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation + logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation + logic FRegWriteE; // Write floating-point register // regfile signals - logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage - logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage - logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding) - logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding) - logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding) - logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding) + logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage + logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage + logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding) + logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding) + logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding) + logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding) // unpacking signals - logic XsE, YsE, ZsE; // input's sign - execute stage - logic XsM, YsM; // input's sign - memory stage - logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage - logic [`NE-1:0] ZeM; // input's exponent - memory stage - logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage - logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage - logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage - logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage - logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage - logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage - logic XSubnormE; // is the input subnormal - logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage - logic XZeroM, YZeroM; // is the input zero - memory stage - logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage - logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage - logic XExpMaxE; // is the exponent all ones (max value) - logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations + logic XsE, YsE, ZsE; // input's sign - execute stage + logic XsM, YsM; // input's sign - memory stage + logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage + logic [`NE-1:0] ZeM; // input's exponent - memory stage + logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage + logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage + logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage + logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage + logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage + logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage + logic XSubnormE; // is the input subnormal + logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage + logic XZeroM, YZeroM; // is the input zero - memory stage + logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage + logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage + logic XExpMaxE; // is the exponent all ones (max value) + logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations // Fma Signals - logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting - logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying - logic [3*`NF+3:0] SmE, SmM; // Sum significand - logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output - logic [`NE+1:0] SeE,SeM; // Sum exponent - logic InvAE, InvAM; // Invert addend - logic AsE, AsM; // Addend sign - logic PsE, PsM; // Product sign - logic SsE, SsM; // Sum sign - logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count + logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting + logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying + logic [3*`NF+3:0] SmE, SmM; // Sum significand + logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output + logic [`NE+1:0] SeE,SeM; // Sum exponent + logic InvAE, InvAM; // Invert addend + logic AsE, AsM; // Addend sign + logic PsE, PsM; // Product sign + logic SsE, SsM; // Sum sign + logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count // Cvt Signals - logic [`NE:0] CeE, CeM; // convert intermediate expoent - logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by - logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal - logic CsE, CsM; // convert result sign - logic IntZeroE, IntZeroM; // is the integer zero? - logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) - logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU) + logic [`NE:0] CeE, CeM; // convert intermediate expoent + logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by + logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal + logic CsE, CsM; // convert result sign + logic IntZeroE, IntZeroM; // is the integer zero? + logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) + logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU) // divide signals - logic [`DIVb:0] QmM; // fdivsqrt signifcand - logic [`NE+1:0] QeM; // fdivsqrt exponent - logic DivStickyM; // fdivsqrt sticky bit - logic FDivDoneE, IFDivStartE; // fdivsqrt control signals - logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU) + logic [`DIVb:0] QmM; // fdivsqrt signifcand + logic [`NE+1:0] QeM; // fdivsqrt exponent + logic DivStickyM; // fdivsqrt sticky bit + logic FDivDoneE, IFDivStartE; // fdivsqrt control signals + logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU) // result and flag signals - logic [`XLEN-1:0] ClassResE; // classify result - logic [`FLEN-1:0] CmpFpResE; // compare result to FPU (min/max) - logic [`XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le) - logic CmpNVE; // compare invalid flag (Not Valid) - logic [`FLEN-1:0] SgnResE; // sign injection result - logic [`XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move) - logic [`FLEN-1:0] PostProcResM; // Postprocessor output - logic [4:0] PostProcFlgM; // Postprocessor flags - logic PreNVE, PreNVM; // selected flag that is ready in the memory stage - logic [`FLEN-1:0] FpResM, FpResW; // FPU preliminary result - logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage - logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register + logic [`XLEN-1:0] ClassResE; // classify result + logic [`FLEN-1:0] CmpFpResE; // compare result to FPU (min/max) + logic [`XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le) + logic CmpNVE; // compare invalid flag (Not Valid) + logic [`FLEN-1:0] SgnResE; // sign injection result + logic [`XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move) + logic [`FLEN-1:0] PostProcResM; // Postprocessor output + logic [4:0] PostProcFlgM; // Postprocessor flags + logic PreNVE, PreNVM; // selected flag that is ready in the memory stage + logic [`FLEN-1:0] FpResM, FpResW; // FPU preliminary result + logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage + logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register // other signals - logic [`FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv - logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed - logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed - logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt - logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer - logic mvsgn; // sign bit for extending move + logic [`FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv + logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed + logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed + logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt + logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer + logic mvsgn; // sign bit for extending move ////////////////////////////////////////////////////////////////////////////////////////// // Decode Stage: fctrl decoder, read register file @@ -180,7 +180,7 @@ module fpu ( fregfile fregfile (.clk, .reset, .we4(FRegWriteW), .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a4(RdW), .wd4(FResultW), - .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); + .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); // D/E pipeline registers flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E); diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 1a5a2eecf..69961a847 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -29,8 +29,8 @@ `include "wally-config.vh" module fregfile ( - input logic clk, reset, - input logic we4, // write enable + input logic clk, reset, + input logic we4, // write enable input logic [4:0] a1, a2, a3, a4, // adresses input logic [`FLEN-1:0] wd4, // write data output logic [`FLEN-1:0] rd1, rd2, rd3 // read data @@ -46,7 +46,7 @@ module fregfile ( always_ff @(negedge clk) // or posedge reset) if (reset) for(i=0; i<32; i++) rf[i] <= 0; - else if (we4) rf[a4] <= wd4; + else if (we4) rf[a4] <= wd4; assign #2 rd1 = rf[a1]; assign #2 rd2 = rf[a2]; diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 0db7dc2f3..9ce938709 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -29,43 +29,43 @@ `include "wally-config.vh" module fsgninj ( - input logic Xs, Ys, // X and Y sign bits - input logic [`FLEN-1:0] X, // X - input logic [`FMTBITS-1:0] Fmt, // format - input logic [1:0] OpCtrl, // operation control - output logic [`FLEN-1:0] SgnRes // result + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result ); - logic ResSgn; // result sign + logic ResSgn; // result sign - // OpCtrl: - // 00 - fsgnj - directly copy over sign value of Y - // 01 - fsgnjn - negate sign value of Y - // 10 - fsgnjx - XOR sign values of X and Y - - // calculate the result's sign - assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys; - - // format final result based on precision - // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - + // OpCtrl: + // 00 - fsgnj - directly copy over sign value of Y + // 01 - fsgnjn - negate sign value of Y + // 10 - fsgnjx - XOR sign values of X and Y + + // calculate the result's sign + assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys; + + // format final result based on precision + // - uses NaN-blocking format + // - if there are any unsused bits the most significant bits are filled with 1s + if (`FPSIZES == 1) - assign SgnRes = {ResSgn, X[`FLEN-2:0]}; + assign SgnRes = {ResSgn, X[`FLEN-2:0]}; else if (`FPSIZES == 2) - assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; + assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; else if (`FPSIZES == 3) begin - logic [2:0] SgnBits; + logic [2:0] SgnBits; always_comb case (Fmt) `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; - `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; `FMT2: SgnBits = {2'b11, ResSgn}; default: SgnBits = {3{1'bx}}; endcase - assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; - end else if (`FPSIZES == 4) begin - logic [3:0] SgnBits; + assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; + end else if (`FPSIZES == 4) begin + logic [3:0] SgnBits; always_comb case (Fmt) `Q_FMT: SgnBits = {ResSgn, X[`D_LEN-1], X[`S_LEN-1], X[`H_LEN-1]}; @@ -73,7 +73,7 @@ module fsgninj ( `S_FMT: SgnBits = {2'b11, ResSgn, X[`H_LEN-1]}; `H_FMT: SgnBits = {3'b111, ResSgn}; endcase - assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]}; - end + assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]}; + end endmodule diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index 0bb30c96a..5a9cf21f0 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -30,13 +30,13 @@ `include "wally-config.vh" module arrs( - input logic clk, - input logic areset, + input logic clk, + input logic areset, output logic reset ); - logic metaStable; - logic resetB; + logic metaStable; + logic resetB; always_ff @(posedge clk , posedge areset) begin if (areset) begin diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index 55f02cff5..c09f98f2c 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -27,9 +27,9 @@ `include "wally-config.vh" module clockgater ( - input logic E, - input logic SE, - input logic CLK, + input logic E, + input logic SE, + input logic CLK, output logic ECLK ); @@ -39,10 +39,10 @@ module clockgater ( // VERY IMPORTANT. // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would. // Do not use this in synthesis! - logic enable_q; + logic enable_q; always_latch begin if(~CLK) begin - enable_q <= E | SE; + enable_q <= E | SE; end end assign ECLK = enable_q & CLK; diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f3c98873e..8905cc551 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -49,39 +49,39 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; - // 64 x 128-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag - genvar index; - // 64 x 44-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + genvar index; + // 64 x 44-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag - genvar index; - // 64 x 22-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + genvar index; + // 64 x 22-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** end else begin: ram integer i; @@ -91,19 +91,18 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( assign dout = RAM[addrd]; /* // Read - always_ff @(posedge clk) - if(ce) dout <= #1 mem[addr]; */ - + always_ff @(posedge clk) + if(ce) dout <= #1 mem[addr]; */ // Write divided into part for bytes and part for extra msbs - // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. - // Therefore these always blocks use the older always @(posedge clk) + // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. + // Therefore these always blocks use the older always @(posedge clk) if(WIDTH >= 8) always @(posedge clk) if (ce & we) for(i = 0; i < WIDTH/8; i++) if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; - + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce & we & bwe[WIDTH/8]) diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 84a3e74f9..55b1d75b0 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x128( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [127:0] D, diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 8e0f56306..5e7a4c5cf 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x22( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [21:0] D, diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 89730a42b..a2c2c81fa 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x44( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [43:0] D, diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index cefd5ab9f..4c72095b6 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -44,96 +44,94 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( output logic [WIDTH-1:0] rd1 ); - logic [WIDTH-1:0] mem[DEPTH-1:0]; - localparam SRAMWIDTH = 32; - localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + logic [WIDTH-1:0] mem[DEPTH-1:0]; + localparam SRAMWIDTH = 32; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; // *************************************************************************** // TRUE Smem macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin - - ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1), .AB(wa2), - .DA('0), - .DB(wd2), - .BWEBA('0), .BWEBB('1), - .QA(rd1), - .QB()); + if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + + ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin - - ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1), .AB(wa2), - .DA('0), - .DB(wd2), - .BWEBA('0), .BWEBB('1), - .QA(rd1), - .QB()); + end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + + ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin - logic [SRAMWIDTH-1:0] SRAMReadData; - logic [SRAMWIDTH-1:0] SRAMWriteData; - logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; - logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; - logic [SRAMWIDTH-1:0] SRAMBitMask; - logic [$clog2(DEPTH)-1:0] RA1Q; - - - onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); - genvar index; - for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux - assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; - assign SRAMWriteData[index*2+1:index*2] = wd2; - assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; - end - flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); - assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; - ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .DA('0), - .DB(SRAMWriteData), - .BWEBA('0), .BWEBB(SRAMBitMask), - .QA(SRAMReadData), - .QB()); + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); - end else begin - - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; - + end else begin + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + // Read logic [$clog2(DEPTH)-1:0] ra1d; flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); assign rd1 = mem[ra1d]; -/* // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; */ - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; - + /* // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; */ + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; end - + endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index b6b501f27..302277ed0 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_1024x36( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [9:0] AA, @@ -43,12 +43,12 @@ module ram2p1r1wbe_1024x36( // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // use part of a larger RAM to avoid generating more flavors of RAM logic [67:0] QAfull, QBfull; TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}), - .BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull)); + .AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}), + .BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull)); assign QA = QAfull[35:0]; assign QB = QBfull[35:0]; diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 108530bee..6da7e06d6 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_1024x68( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [9:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_1024x68( // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index 49d2631ee..e181fdd07 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_128x64( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [6:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_128x64( // replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, -// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 14fbea75c..442eff90d 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_2048x64( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [8:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_2048x64( // replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, -// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index e551099f4..4236bb3f6 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_64x32( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [5:0] AA, @@ -43,7 +43,7 @@ module ram2p1r1wbe_64x32( // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 6930bc0db..ef9c6da37 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -28,8 +28,8 @@ `include "wally-config.vh" module rom1p1r #(parameter ADDR_WIDTH = 8, - parameter DATA_WIDTH = 32, - parameter PRELOAD_ENABLED = 0) + parameter DATA_WIDTH = 32, + parameter PRELOAD_ENABLED = 0) (input logic clk, input logic ce, input logic [ADDR_WIDTH-1:0] addr, @@ -37,7 +37,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ); // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; /* if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); @@ -46,55 +46,55 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, end else begin */ always @ (posedge clk) begin - if(ce) dout <= ROM[addr]; + if(ce) dout <= ROM[addr]; end // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) initial begin - ROM[0] = 64'h9581819300002197; - ROM[1] = 64'h4281420141014081; - ROM[2] = 64'h4481440143814301; - ROM[3] = 64'h4681460145814501; - ROM[4] = 64'h4881480147814701; - ROM[5] = 64'h4a814a0149814901; - ROM[6] = 64'h4c814c014b814b01; - ROM[7] = 64'h4e814e014d814d01; - ROM[8] = 64'h0110011b4f814f01; - ROM[9] = 64'h059b45011161016e; - ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h05a000ef8006061b; - ROM[12] = 64'h0ff003930000100f; - ROM[13] = 64'h4e952e3110060e37; - ROM[14] = 64'hc602829b0053f2b7; - ROM[15] = 64'h2023fe02dfe312fd; - ROM[16] = 64'h829b0053f2b7007e; - ROM[17] = 64'hfe02dfe312fdc602; - ROM[18] = 64'h4de31efd000e2023; - ROM[19] = 64'h059bf1402573fdd0; - ROM[20] = 64'h0000061705e20870; - ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h11010002806702fe; - ROM[23] = 64'h84b2842ae426e822; - ROM[24] = 64'h892ee04aec064511; - ROM[25] = 64'h06e000ef07e000ef; - ROM[26] = 64'h979334fd02905563; - ROM[27] = 64'h07930177d4930204; - ROM[28] = 64'h4089093394be2004; - ROM[29] = 64'h04138522008905b3; - ROM[30] = 64'h19e3014000ef2004; - ROM[31] = 64'h64a2644260e2fe94; - ROM[32] = 64'h6749808261056902; - ROM[33] = 64'hdfed8b8510472783; - ROM[34] = 64'h2423479110a73823; - ROM[35] = 64'h10472783674910f7; - ROM[36] = 64'h20058693ffed8b89; - ROM[37] = 64'h05a1118737836749; - ROM[38] = 64'hfed59be3fef5bc23; - ROM[39] = 64'h1047278367498082; - ROM[40] = 64'h47858082dfed8b85; - ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; + ROM[0] = 64'h9581819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h05a000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h11010002806702fe; + ROM[23] = 64'h84b2842ae426e822; + ROM[24] = 64'h892ee04aec064511; + ROM[25] = 64'h06e000ef07e000ef; + ROM[26] = 64'h979334fd02905563; + ROM[27] = 64'h07930177d4930204; + ROM[28] = 64'h4089093394be2004; + ROM[29] = 64'h04138522008905b3; + ROM[30] = 64'h19e3014000ef2004; + ROM[31] = 64'h64a2644260e2fe94; + ROM[32] = 64'h6749808261056902; + ROM[33] = 64'hdfed8b8510472783; + ROM[34] = 64'h2423479110a73823; + ROM[35] = 64'h10472783674910f7; + ROM[36] = 64'h20058693ffed8b89; + ROM[37] = 64'h05a1118737836749; + ROM[38] = 64'hfed59be3fef5bc23; + ROM[39] = 64'h1047278367498082; + ROM[40] = 64'h47858082dfed8b85; + ROM[41] = 64'h40a7853b4015551b; + ROM[42] = 64'h808210a7a02367c9; end endmodule diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index bc16a76dc..ea5b92054 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -26,7 +26,7 @@ module rom1p1r_128x32( input logic CLK, - input logic CEB, + input logic CEB, input logic [6:0] A, output logic [31:0] Q ); diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 3c7ea4842..6712d10fa 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -25,14 +25,14 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rom1p1r_128x64( - input logic CLK, - input logic CEB, + input logic CLK, + input logic CEB, input logic [6:0] A, output logic [63:0] Q ); // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor -ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q); + ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q); // generic64x128ROM romIP (.CLK, .CEB, .A, .Q); endmodule diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b436fda46..90d031a14 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" module bmuctrl( - input logic clk, reset, + input logic clk, reset, // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage @@ -43,7 +43,7 @@ module bmuctrl( output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals - input logic StallE, FlushE, // Stall, flush Execute stage + input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectD, // ALU select output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal @@ -66,7 +66,7 @@ module bmuctrl( `define BMUCTRLW 17 - logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals + logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals // Extract fields assign OpD = InstrD[6:0]; @@ -180,4 +180,4 @@ module bmuctrl( // BMU Execute stage pipieline control register flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 21811b49a..da99a48f6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -31,7 +31,7 @@ module controller( - input logic clk, reset, + input logic clk, reset, // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage @@ -41,11 +41,11 @@ module controller( output logic JumpD, // Jump instruction output logic BranchD, // Branch instruction // Execute stage control signals - input logic StallE, FlushE, // Stall, flush Execute stage + input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] FlagsE, // Comparison flags ({eq, lt}) input logic FWriteIntE, // Write integer register, coming from FPU controller output logic PCSrcE, // Select signal to choose next PC (for datapath and Hazard unit) - output logic ALUSrcAE, ALUSrcBE, // ALU operands + output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) @@ -74,7 +74,7 @@ module controller( output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals input logic StallW, FlushW, // Stall, flush Writeback stage - output logic RegWriteW, IntDivW, // Instruction writes a register, is an integer divide + output logic RegWriteW, IntDivW, // Instruction writes a register, is an integer divide output logic [2:0] ResultSrcW, // Select source of result to write back to register file // Stall during CSRs output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions @@ -89,16 +89,16 @@ module controller( `define CTRLW 23 // pipelined control signals - logic RegWriteD, RegWriteE; // RegWrite (register will be written) + logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) - logic BaseW64D; // W64 for Base instructions specifically - logic BaseRegWriteD; // Indicates if Base instruction register write instruction - logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu + logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) + logic BaseW64D; // W64 for Base instructions specifically + logic BaseRegWriteD; // Indicates if Base instruction register write instruction + logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic BaseALUSrcBD; // Base instruction ALU B source select signal logic [2:0] ALUControlD; // Determines ALU operation - logic ALUSrcAD, ALUSrcBD; // ALU inputs + logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR logic CSRReadD; // CSR read instruction @@ -115,7 +115,7 @@ module controller( logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; - logic BranchFlagE; // Branch flag to use (chosen between eq or lt) + logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers @@ -146,29 +146,29 @@ module controller( logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD; logic Funct7ShiftZeroD, Funct7Shiftb5D; - assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions - assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub + assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions + assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub assign Funct7ShiftZeroD = (`XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; assign Funct7Shiftb5D = (`XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; - assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms - assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); - assign IFunctD = IShiftD | INoShiftD; - assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD; - assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv - assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | - ((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); - assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | - ((`XLEN == 64) & (Funct3D == 3'b011)); - assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches - assign JFunctD = (Funct3D == 3'b000); + assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms + assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); + assign IFunctD = IShiftD | INoShiftD; + assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD; + assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv + assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | + ((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); + assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | + ((`XLEN == 64) & (Funct3D == 3'b011)); + assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches + assign JFunctD = (Funct3D == 3'b000); end else begin:legalcheck2 - assign IFunctD = 1; // Don't bother to separate out shift decoding - assign RFunctD = ~Funct7D[0]; // Not a multiply - assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv - assign LFunctD = 1; // don't bother to check Funct3 for loads - assign SFunctD = 1; // don't bother to check Funct3 for stores - assign BFunctD = 1; // don't bother to check Funct3 for branches - assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign IFunctD = 1; // Don't bother to separate out shift decoding + assign RFunctD = ~Funct7D[0]; // Not a multiply + assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv + assign LFunctD = 1; // don't bother to check Funct3 for loads + assign SFunctD = 1; // don't bother to check Funct3 for stores + assign BFunctD = 1; // don't bother to check Funct3 for branches + assign JFunctD = 1; // don't bother to check Funct3 for jumps end // Main Instruction Decoder @@ -182,7 +182,7 @@ module controller( 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported 7'b0001111: if (`ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence - else + else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU @@ -337,4 +337,4 @@ module controller( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD)); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index a6fb1fdcd..a48b39402 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -108,7 +108,7 @@ module datapath ( flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - + mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); @@ -121,7 +121,7 @@ module datapath ( // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); - flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); + flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); // Writeback stage pipeline register and logic diff --git a/src/ieu/forward.sv b/src/ieu/forward.sv index 8bfaa51c6..62cc5ea4f 100644 --- a/src/ieu/forward.sv +++ b/src/ieu/forward.sv @@ -34,7 +34,7 @@ module forward( input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers input logic MemReadE, MDUE, CSRReadE, // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE) input logic RegWriteM, RegWriteW, // Instruction in Memory or Writeback stage writes register file - input logic FCvtIntE, // FPU convert float to int + input logic FCvtIntE, // FPU convert float to int input logic SCE, // Store Conditional instruction // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 0fdba9e8a..d5b3e8f40 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -29,27 +29,27 @@ `include "wally-config.vh" module ieu ( - input logic clk, reset, + input logic clk, reset, // Decode stage signals - input logic [31:0] InstrD, // Instruction - input logic IllegalIEUFPUInstrD, // Illegal instruction - output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers + input logic [31:0] InstrD, // Instruction + input logic IllegalIEUFPUInstrD, // Illegal instruction + output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers // Execute stage signals input logic [`XLEN-1:0] PCE, // PC input logic [`XLEN-1:0] PCLinkE, // PC + 4 - output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) - input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int + output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) + input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int output logic [`XLEN-1:0] IEUAdrE, // Memory address - output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction - output logic [2:0] Funct3E, // Funct3 instruction field + output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction + output logic [2:0] Funct3E, // Funct3 instruction field output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register // Memory stage signals - input logic SquashSCW, // Squash store conditional, from LSU - output logic [1:0] MemRWM, // Read/write control goes to LSU - output logic [1:0] AtomicM, // Atomic control goes to LSU + input logic SquashSCW, // Squash store conditional, from LSU + output logic [1:0] MemRWM, // Read/write control goes to LSU + output logic [1:0] AtomicM, // Atomic control goes to LSU output logic [`XLEN-1:0] WriteDataM, // Write data to LSU - output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU + output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU output logic [`XLEN-1:0] SrcAM, // ALU SrcA to Privileged unit and FPU output logic [4:0] RdM, // Destination register input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) @@ -66,12 +66,12 @@ module ieu ( output logic [4:0] RdW, // Destination register input logic [`XLEN-1:0] ReadDataW, // LSU's read data // Hazard unit signals - input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit - input logic FlushD, FlushE, FlushM, FlushW, // Flush signals - output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit + input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit + input logic FlushD, FlushE, FlushM, FlushW, // Flush signals + output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit output logic MDUStallD, CSRRdStallD, StoreStallD, - output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction - output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions + output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction + output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions ); logic [2:0] ImmSrcD; // Select type of immediate extension diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index cc0439c08..a4ee1cc3e 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -52,7 +52,7 @@ module regfile ( always_ff @(negedge clk) if (reset) for(i=1; i Date: Fri, 24 Mar 2023 17:57:02 -0500 Subject: [PATCH 13/54] Renamed controllerinputstage to controllerinput to match book. --- src/ebu/{controllerinputstage.sv => controllerinput.sv} | 2 +- src/ebu/ebu.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename src/ebu/{controllerinputstage.sv => controllerinput.sv} (99%) diff --git a/src/ebu/controllerinputstage.sv b/src/ebu/controllerinput.sv similarity index 99% rename from src/ebu/controllerinputstage.sv rename to src/ebu/controllerinput.sv index 7a6c76bb9..a8c8e8308 100644 --- a/src/ebu/controllerinputstage.sv +++ b/src/ebu/controllerinput.sv @@ -33,7 +33,7 @@ `include "wally-config.vh" -module controllerinputstage #( +module controllerinput #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( input logic HCLK, diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index b045c6aaa..8dddff35a 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -98,14 +98,14 @@ module ebu ( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinputstage #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), From 78ab9f59afcdba92fc00fa1ea79091fdeee02db6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 18:55:43 -0500 Subject: [PATCH 14/54] Updated GPIO signal names to reflect book. --- fpga/src/fpgaTop.v | 12 ++++++------ src/uncore/gpio_apb.sv | 12 ++++++------ src/uncore/uncore.sv | 8 ++++---- src/wally/wallypipelinedsoc.sv | 8 ++++---- testbench/testbench-linux.sv | 8 ++++---- testbench/testbench.sv | 6 +++--- testbench/testbench_imperas.sv | 6 +++--- 7 files changed, 30 insertions(+), 30 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74e..990495f44 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -88,7 +88,7 @@ module fpgaTop - wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + wire [31:0] GPIOIN, GPIOOUT, GPIOEN; wire SDCCmdIn; wire SDCCmdOE; @@ -183,8 +183,8 @@ module fpgaTop - assign GPIOPinsIn = {28'b0, GPI}; - assign GPO = GPIOPinsOut[4:0]; + assign GPIOIN = {28'b0, GPI}; + assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; @@ -231,9 +231,9 @@ module fpgaTop .HMASTLOCK(HMASTLOCK), .HREADY(HREADY), // GPIO - .GPIOPinsIn(GPIOPinsIn), - .GPIOPinsOut(GPIOPinsOut), - .GPIOPinsEn(GPIOPinsEn), + .GPIOIN(GPIOIN), + .GPIOOUT(GPIOOUT), + .GPIOEN(GPIOEN), // UART .UARTSin(UARTSin), .UARTSout(UARTSout), diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 7a8ac3c14..869f1bbdd 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -41,8 +41,8 @@ module gpio_apb ( output logic [`XLEN-1:0] PRDATA, output logic PREADY, input logic [31:0] iof0, iof1, - input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic [31:0] GPIOIN, + output logic [31:0] GPIOOUT, GPIOEN, output logic GPIOIntr ); @@ -138,8 +138,8 @@ module gpio_apb ( // chip i/o // connect OUT to IN for loopback testing - if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en; - else assign input0d = GPIOPinsIn & input_en; + if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en; + else assign input0d = GPIOIN & input_en; // synchroninzer for inputs flop #(32) sync1(PCLK,input0d,input1d); @@ -148,8 +148,8 @@ module gpio_apb ( assign input_val = input3d; assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0 assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val - assign GPIOPinsOut = gpio_out ^ out_xor; // per-bit flip output polarity - assign GPIOPinsEn = output_en; + assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity + assign GPIOEN = output_en; assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)}; endmodule diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 2aeb81048..4f00a3da4 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -51,8 +51,8 @@ module uncore ( output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT output logic MExtInt, SExtInt, // External interrupts from PLIC output logic [63:0] MTIME_CLINT, // MTIME, from CLINT - input logic [31:0] GPIOPinsIn, // GPIO pin input value - output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable + input logic [31:0] GPIOIN, // GPIO pin input value + output logic [31:0] GPIOOUT, GPIOEN, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output output logic SDCCmdOut, // SD Card command output @@ -133,9 +133,9 @@ module uncore ( gpio_apb gpio( .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), - .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr); + .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr); end else begin : gpio - assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; + assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end if (`UART_SUPPORTED == 1) begin : uart uart_apb uart( diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ea9752081..0e3632451 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -51,9 +51,9 @@ module wallypipelinedsoc ( output logic HREADY, // I/O Interface input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output input logic SDCCmdIn, // SDC Command input @@ -85,7 +85,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .MTIME_CLINT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); end diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 1705b36fd..908660ffe 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -252,8 +252,8 @@ module testbench; logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; logic UARTSin, UARTSout; // FPGA-specific Stuff @@ -264,7 +264,7 @@ module testbench; logic [3:0] SDCDatIn; // Hardwire UART, GPIO pins - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; // Wally @@ -272,7 +272,7 @@ module testbench; .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b546f88b3..bb70a6360 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -150,7 +150,7 @@ logic [3:0] dummy; string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -169,7 +169,7 @@ logic [3:0] dummy; logic InReset; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -199,7 +199,7 @@ logic [3:0] dummy; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 6ac11bc2d..f63c640d7 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -73,7 +73,7 @@ module testbench; string testName; string memfilename, testDir, adrstr, elffilename; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -217,7 +217,7 @@ module testbench; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -247,7 +247,7 @@ module testbench; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions From c10d98b1c8ec186d4ff4193716d7a71a76b9d8a4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 19:09:36 -0500 Subject: [PATCH 15/54] Updated fpga constraints to remove critical warning. --- fpga/constraints/marked_debug.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 97ac1ead3..6e6da0128 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -120,8 +120,6 @@ ebu/ebu.sv: logic HCLK ebu/ebu.sv: logic HREADY ebu/ebu.sv: logic HRESP ebu/ebu.sv: logic HADDR -ebu/ebu.sv: logic HWDATA -ebu/ebu.sv: logic HWSTRB ebu/ebu.sv: logic HWRITE ebu/ebu.sv: logic HSIZE ebu/ebu.sv: logic HBURST From 3fc0c4b34ed1a73eac203abee8af59207dcaae56 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 20:37:48 -0500 Subject: [PATCH 16/54] Modified plic and uart to remove async reset. This removes vivado critical warning. --- src/uncore/plic_apb.sv | 2 +- src/uncore/uartPC16550D.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8132fa371..7231f609b 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -97,7 +97,7 @@ module plic_apb ( // ================== // Register Interface // ================== - always @(posedge PCLK,negedge PRESETn) begin + always @(posedge PCLK) begin // resetting if (~PRESETn) begin intPriority <= #1 {`N{3'b0}}; diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index b33c4962d..a2255af5d 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -290,7 +290,7 @@ module uartPC16550D( assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time // receive FIFO and register - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; end else begin From c8baffba7c30f9f44c9473122c6f8028ffef4f86 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 20:38:13 -0500 Subject: [PATCH 17/54] Started constrains file for arty a7 fpga. --- fpga/constraints/constraints-artyA7.xdc | 251 ++++++++++++++++++++++++ 1 file changed, 251 insertions(+) create mode 100644 fpga/constraints/constraints-artyA7.xdc diff --git a/fpga/constraints/constraints-artyA7.xdc b/fpga/constraints/constraints-artyA7.xdc new file mode 100644 index 000000000..866d78c96 --- /dev/null +++ b/fpga/constraints/constraints-artyA7.xdc @@ -0,0 +1,251 @@ +# The main clocks are all autogenerated by the Xilinx IP +# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. +# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. +# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. + +create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] + +##### GPI #### +set_property PACKAGE_PIN D9 [get_ports {GPI[0]}] +set_property PACKAGE_PIN C9 [get_ports {GPI[1]}] +set_property PACKAGE_PIN B9 [get_ports {GPI[2]}] +set_property PACKAGE_PIN B8 [get_ports {GPI[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] +set_max_delay -from [get_ports {GPI[*]}] 10.000 + +##### GPO #### +set_property PACKAGE_PIN G6 [get_ports {GPO[0]}] +set_property PACKAGE_PIN F6 [get_ports {GPO[1]}] +set_property PACKAGE_PIN E1 [get_ports {GPO[2]}] +set_property PACKAGE_PIN G3 [get_ports {GPO[4]}] +set_property PACKAGE_PIN J4 [get_ports {GPO[3]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}] +set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}] +set_max_delay -to [get_ports {GPO[*]}] 10.000 +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}] + + +##### UART ##### +# *** IOSTANDARD is probably wrong +set_property PACKAGE_PIN A9 [get_ports UARTSin] +set_property PACKAGE_PIN D0 [get_ports UARTSout] +set_max_delay -from [get_ports UARTSin] 10.000 +set_max_delay -to [get_ports UARTSout] 10.000 +set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] +set_property IOSTANDARD LVCMOS3 [get_ports UARTSout] +set_property DRIVE 6 [get_ports UARTSout] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout] + + +##### reset ##### +#************** reset is inverted +set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] +set_max_delay -from [get_ports reset] 15.000 +set_false_path -from [get_ports reset] +set_property PACKAGE_PIN C2 [get_ports {reset}] +set_property IOSTANDARD LVCMOS33 [get_ports {reset}] + + + +##### cpu_reset ##### +# *********** +set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}] +set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] + + +##### calib ##### +# ********** +set_property PACKAGE_PIN BA37 [get_ports calib] +set_property IOSTANDARD LVCMOS12 [get_ports calib] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib] +set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000 + + +##### ahblite_resetn ##### +# *************** +set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}] +set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}] + + +##### south_rst ##### +# *********************** +set_property PACKAGE_PIN BE22 [get_ports south_rst] +set_property IOSTANDARD LVCMOS18 [get_ports south_rst] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst] + + +##### SD Card I/O ##### +#***** may have to switch to Pmod JB or JC. +set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}] +set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}] +set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}] +set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}] +set_property PACKAGE_PIN F2 [get_ports SDCCLK] +set_property PACKAGE_PIN D3 [get_ports {SDCCmd}] + +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] +set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}] +set_property PULLUP true [get_ports {SDCDat[3]}] +set_property PULLUP true [get_ports {SDCDat[2]}] +set_property PULLUP true [get_ports {SDCDat[1]}] +set_property PULLUP true [get_ports {SDCDat[0]}] +set_property PULLUP true [get_ports {SDCCmd}] + + +set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] + +set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] + + +set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] + +set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] + +# ********************************* +set_property DCI_CASCADE {64} [get_iobanks 65] +set_property INTERNAL_VREF 0.9 [get_iobanks 65] + +# ddr3 + +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1] +set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0] +set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0] + + +set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] +set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]] +set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]] +set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]] +set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]] +set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]] +set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]] +set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]] +set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]] +set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]] +set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]] +set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]] +set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]] +set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]] +set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]] +set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]] +set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]] +set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]] +set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]] +set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]] +set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]] +set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]] +set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]] +set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]] +set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]] +set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]] +set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]] +set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]] +set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]] +set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]] +set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]] +set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]] +set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]] +set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]] +set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]] +set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]] +set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]] +set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]] +set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]] +set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]] +set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]] +set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n] +set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n] +set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n] +set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n] +set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] +set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] +set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] + + + +set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 + + +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] + + + +set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000 + + From e65cbc6636c1ea7dcc7e9bbbba09f1c414273574 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 27 Mar 2023 09:46:16 +0100 Subject: [PATCH 18/54] update to allow running of ImperasDV with linux boot optimize performance of the tracer --- config/buildroot/wally-config.vh | 2 +- sim/imperas.ic | 6 ++---- sim/run-imperas-linux.sh | 2 +- testbench/testbench-linux-imperas.sv | 3 --- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index 3a68571dd..236574288 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -29,7 +29,7 @@ `include "wally-shared.vh" `define FPGA 1 -`define QEMU 1 +`define QEMU 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/sim/imperas.ic b/sim/imperas.ic index 82aedf1c9..167c0cc44 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,4 +1,4 @@ -#--mpdconsole refRoot +#--mpdconsole #--gdbconsole --showoverrides --showcommands @@ -18,8 +18,6 @@ # illegal pmp read contained this # --override cpu/tval_ii_code=F ---registerset cpu/SCOUNTEREN=0x1 - # PMA Settings # 'r': read access allowed # 'w': write access allowed @@ -51,7 +49,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 5a21b0ebe..09face55e 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -4,6 +4,6 @@ export RISCV=/scratch/moore/RISCV export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" -export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 64f745e49..201042084 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -336,9 +336,6 @@ module testbench; void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx end - // ERROR Temporary as it powers up as 0x1 - void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason - // cannot predict this register due to latency between // pending and taken void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP From 86ab90d715923ee595056ed3f50e3f6d9dc54855 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 27 Mar 2023 06:34:45 -0700 Subject: [PATCH 19/54] Commented out setting RISCV in run-imperas-linux.sh --- sim/run-imperas-linux.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 09face55e..00e9845cf 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -1,6 +1,6 @@ #!/bin/bash -export RISCV=/scratch/moore/RISCV +#export RISCV=/scratch/moore/RISCV export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" From edaa30624082d75f274ab17e26956ddd20a7d346 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 27 Mar 2023 09:52:38 -0700 Subject: [PATCH 20/54] Removed unnecessary monitor --- src/privileged/csrsr.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 1a4b6caa3..92efebbf7 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -53,8 +53,6 @@ module csrsr ( logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE; logic nextMBE, nextSBE; - initial $monitor("QEMU=%0d STATUS_SXL=%0d STATUS_UXL=%0d", `QEMU, STATUS_SXL, STATUS_UXL); - // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 // Lower privilege status registers are a subset of the full status register From 4e2131066d15d4ec37df4513a7e51c0377eae319 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 14:45:55 -0500 Subject: [PATCH 21/54] Added buildroot instructions back to readme. moved these instructions to the docs directory. --- docs/README-linux.md | 40 ++++++++++++++++++++++++++++ testbench/testbench-linux-imperas.sv | 6 ++--- 2 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 docs/README-linux.md diff --git a/docs/README-linux.md b/docs/README-linux.md new file mode 100644 index 000000000..cf9c146dc --- /dev/null +++ b/docs/README-linux.md @@ -0,0 +1,40 @@ +### Cross-Compile Buildroot Linux + +Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. + +Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. + +To configure and build Buildroot: + + $ cd $RISCV + $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now + $ git clone https://github.com/buildroot/buildroot.git + $ cd buildroot + $ git checkout 2021.05 # last tested working version + $ cp -r $WALLY/linux/buildroot-config-src/wally ./board + $ cp ./board/wally/main.config .config + $ make --jobs + +To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. + +$ source ~/riscv-wally/setup.sh +$ cd $WALLY/linux/buildroot-scripts +$ make all + +Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. + +### Generate load images for linux boot + +The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors + + cd cvw/linux/testvector-generation + ./genInitMem.sh + +This may require changing file permissions to the linux-testvectors directory. + +### Generate QEMU linux trace + +The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours. + + cd cvw/linux/testvector-generation + ./genTrace.sh diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 201042084..00167e5fd 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -263,8 +263,8 @@ module testbench; logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; logic UARTSin, UARTSout; // FPGA-specific Stuff @@ -430,7 +430,7 @@ module testbench; .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); From dd503c22ea79e0a56bda304525b38c16aaf1eea3 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini <78130750+magpyed@users.noreply.github.com> Date: Mon, 27 Mar 2023 13:35:48 -0700 Subject: [PATCH 22/54] Fixing order of local repo commands in README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a03625217..9cb56de0d 100644 --- a/README.md +++ b/README.md @@ -34,8 +34,8 @@ Clone your fork of the repo and run the setup script. $ cd $ git clone --recurse-submodules https://github.com//cvw - $ git remote add upstream https://github.com/openhwgroup/cvw $ cd cvw + $ git remote add upstream https://github.com/openhwgroup/cvw $ source ./setup.sh Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. From a0aac6b15cac367c37d8bd75727338bf3ffb5280 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Mon, 27 Mar 2023 13:47:26 -0700 Subject: [PATCH 23/54] add tests/coverage/ tests as a target to sim/Makefile --- sim/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sim/Makefile b/sim/Makefile index bf6255b33..540c9418f 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles +all: riscoftests memfiles coveragetests # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -50,3 +50,6 @@ riscoftests: make -C ../tests/riscof/ memfiles: make -f makefile-memfile wally-sim-files --jobs + +coveragetests: + make -C ../tests/coverage/ From 498a17dedafe1ed9b2ed05ba7cd2da6aaa4b17e1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:06:20 -0500 Subject: [PATCH 24/54] Added some additional details about the buildroot install. --- docs/README-linux.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/README-linux.md b/docs/README-linux.md index cf9c146dc..63a3f5e2b 100644 --- a/docs/README-linux.md +++ b/docs/README-linux.md @@ -16,6 +16,7 @@ To configure and build Buildroot: $ make --jobs To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. +Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories. $ source ~/riscv-wally/setup.sh $ cd $WALLY/linux/buildroot-scripts From 510a0bb3baf3d883bf4c2b05ca332c688d9bedc0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:36:02 -0500 Subject: [PATCH 25/54] First stab at the i cache logger. --- testbench/testbench.sv | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index bb70a6360..575b9b6c5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,6 +30,7 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 +`define INSTR_FETCH_ADDR_LOGGER 0 module testbench; parameter DEBUG=0; @@ -546,7 +547,29 @@ logic [3:0] dummy; end end end +end + + + if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("ICache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end end + if (`BPRED_SUPPORTED == 1) begin From 108ad671cf5ea479a0cf77fe9d61999edca66bc1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 23:44:50 -0500 Subject: [PATCH 26/54] Now reports i cache and d cache memory accesses. --- testbench/testbench.sv | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 575b9b6c5..f07cfef12 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,7 +30,8 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 -`define INSTR_FETCH_ADDR_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 1 +`define D_CACHE_ADDR_LOGGER 1 module testbench; parameter DEBUG=0; @@ -550,7 +551,7 @@ logic [3:0] dummy; end - if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + if (`I_CACHE_ADDR_LOGGER == 1) begin int file; string LogFile; logic resetD, resetEdge; @@ -563,15 +564,41 @@ end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(dut.core.StallD & ~dut.core.FlushD) begin - $fwrite(file, "%h R\n", dut.core.ifu.PCF); + if(~dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCPF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + + if (`D_CACHE_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("DCache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin + $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin + $fwrite(file, "%h W\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change + $fwrite(file, "%h A\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.FlushDCache) begin + $fwrite(file, "%h F\n", dut.core.lsu.PAdrM); + end end if(EndSample) $fwrite(file, "END %s\n", memfilename); end end - - if (`BPRED_SUPPORTED == 1) begin if (`BPRED_LOGGER) begin string direction; From 20ebf7e536ce5ef50ff892447f25f440d4621aa8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 04:37:56 -0700 Subject: [PATCH 27/54] CSRS privileged coverage test --- src/privileged/csrs.sv | 2 +- testbench/tests.vh | 3 ++- tests/coverage/priv.S | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 tests/coverage/priv.S diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index a50ef2990..3d75ef73e 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -131,7 +131,7 @@ module csrs #(parameter SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin CSRSReadValM = 0; - if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; + IllegalCSRSAccessM = 1; end SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; STIMECMP: if (`SSTC_SUPPORTED & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[`XLEN-1:0]; diff --git a/testbench/tests.vh b/testbench/tests.vh index 93c1d7ea1..478cd3cdf 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -46,7 +46,8 @@ string tvpaths[] = '{ `COVERAGE, "ieu", "ebu", - "csrwrites" + "csrwrites", + "priv" }; string coremark[] = '{ diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S new file mode 100644 index 000000000..81ec31df9 --- /dev/null +++ b/tests/coverage/priv.S @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// priv.S +// +// Written: David_Harris@hmc.edu 23 March 2023 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + # switch to supervisor mode + li a0, 1 + ecall + + # Test read to stimecmp fails when MCOUNTEREN_TM is not set + csrr t0, stimecmp + + j done From 01113320f4235ebe3eb8da8e668c906b9be840d6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 06:46:11 -0700 Subject: [PATCH 28/54] Set PMP to allow all user/supervisor accesses in WALLY-init-lib --- tests/coverage/WALLY-init-lib.h | 4 ++++ tests/coverage/priv.S | 1 + 2 files changed, 5 insertions(+) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 4de5e7688..f95ef285c 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -40,6 +40,10 @@ rvtest_entry_point: la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable + # set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 81ec31df9..3aa3aea5c 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -33,6 +33,7 @@ main: ecall # Test read to stimecmp fails when MCOUNTEREN_TM is not set + addi t0, zero, 0 csrr t0, stimecmp j done From 39d3bf8e8ae905d480f18a417b3e3a892fa157fd Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 06:58:17 -0700 Subject: [PATCH 29/54] Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests --- src/mmu/pmpadrdec.sv | 3 +-- src/mmu/pmpchecker.sv | 7 ++----- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 6 ++++++ .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 5e63e7c65..f36fa99fc 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -38,7 +38,7 @@ module pmpadrdec ( input logic [`PA_BITS-3:0] PMPAdr, input logic PAgePMPAdrIn, output logic PAgePMPAdrOut, - output logic Match, Active, + output logic Match, output logic L, X, W, R ); @@ -84,7 +84,6 @@ module pmpadrdec ( assign X = PMPCfg[2]; assign W = PMPCfg[1]; assign R = PMPCfg[0]; - assign Active = |PMPCfg[4:3]; // known bug: The size of the access is not yet checked. For example, if an NA4 entry matches 0xC-0xF and the system // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index b75824257..c1c9641fa 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -53,7 +53,6 @@ module pmpchecker ( logic EnforcePMP; // should PMP be checked in this privilege level logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address. - logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] @@ -64,14 +63,12 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .Match, .Active, .L, .X, .W, .R); + .Match, .L, .X, .W, .R); priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; -// assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode -// *** remove unused Active lines from pmpadrdecs + assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index f3f963d8b..277f67274 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -55,6 +55,12 @@ RVTEST_CODE_BEGIN csrw sscratch, sp la sp, stack_top + // set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses + + .endm // Code to trigger traps goes here so we have consistent mtvals for instruction adresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 85b5ab8c4..44a4ea66f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -57,6 +57,11 @@ RVTEST_CODE_BEGIN csrw sscratch, sp la sp, stack_top + // set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses + .endm // Code to trigger traps goes here so we have consistent mtvals for instruction adresses From aa31b45d8869e3a56c0838c2154bc53be5fa08ac Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 08:35:23 -0700 Subject: [PATCH 30/54] Fixed RV32 tests after PMP fix --- src/mmu/mmu.sv | 4 ++-- src/mmu/pmpchecker.sv | 3 ++- .../references/WALLY-trap-01.reference_output | 12 ++++++------ .../references/WALLY-trap-s-01.reference_output | 12 ++++++------ .../references/WALLY-trap-u-01.reference_output | 12 ++++++------ .../references/WALLY-trap-01.reference_output | 12 ++++++------ .../references/WALLY-trap-s-01.reference_output | 12 ++++++------ .../references/WALLY-trap-u-01.reference_output | 12 ++++++------ 8 files changed, 40 insertions(+), 39 deletions(-) diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 4accf0cbc..ffd01c440 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -108,12 +108,12 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .Cacheable, .Idempotent, .SelTIM, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); - if (`PMP_ENTRIES > 0) + if (`PMP_ENTRIES > 0) begin : pmp pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); - else begin + end else begin assign PMPInstrAccessFaultF = 0; assign PMPStoreAmoAccessFaultM = 0; assign PMPLoadAccessFaultM = 0; diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index c1c9641fa..e7c660ca0 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -56,7 +56,7 @@ module pmpchecker ( logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] - if (`PMP_ENTRIES > 0) // prevent complaints about array of no elements when PMP_ENTRIES = 0 + if (`PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0 pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( .PhysicalAddress, .PMPCfg(PMPCFG_ARRAY_REGW), @@ -64,6 +64,7 @@ module pmpchecker ( .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), .Match, .L, .X, .W, .R); + end priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index 2877f4a8e..a9c3da2c0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -6,16 +6,16 @@ 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -8000015c # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000165 # mtval of misaligned address +80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -8000017d # mtval of address with misaligned store instr +80000189 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) @@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -8000015c # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000165 # mtval of misaligned address +80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -8000017d # mtval of address with misaligned store instr +80000189 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 5ee52bee5..e57184719 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -60,16 +60,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 22699f42f..5c6d8378d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -8000015c # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction adress 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000165 # stval of misaligned address +80000171 # stval of misaligned address 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -8000017d # stval of address with misaligned store instr +80000189 # stval of address with misaligned store instr 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index d77998a66..78e096cee 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -14,13 +14,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003f4 # mtval of breakpoint instruction adress (0x80000400) +80000408 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003fd # mtval of misaligned address (0x80000409) +80000411 # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -32,7 +32,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000415 # mtval of address with misaligned store instr (0x80000421) +80000429 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -126,13 +126,13 @@ ffffffff 00000000 00000003 # mcause from Breakpoint 00000000 -800003f4 # mtval of breakpoint instruction adress (0x80000400) +80000408 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003fd # mtval of misaligned address (0x80000409) +80000411 # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -144,7 +144,7 @@ ffffffff 00000000 00000006 # mcause from store misaligned 00000000 -80000415 # mtval of address with misaligned store instr (0x80000421) +80000429 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index cdc883697..dc5acb4d6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -122,13 +122,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -140,7 +140,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 39f874ef7..7afec5268 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -116,13 +116,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -800003f4 # stval of breakpoint instruction adress (0x80000400) +80000408 # stval of breakpoint instruction adress (0x80000400) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -800003fd # stval of misaligned address (0x80000409) +80000411 # stval of misaligned address (0x80000409) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -134,7 +134,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000415 # stval of address with misaligned store instr (0x80000421) +80000429 # stval of address with misaligned store instr (0x80000421) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 From 20d8c2476e5877a9cd9dd96392abe1862972e794 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 09:08:48 -0700 Subject: [PATCH 31/54] Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP --- testbench/tests.vh | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 478cd3cdf..79f100d4f 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1964,17 +1964,19 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", "rv32i_m/privilege/src/WALLY-endianness-01.S", - "rv32i_m/privilege/src/WALLY-satp-invalid-01.S" - }; - - string wally32periph[] = '{ - `WALLYTEST, - "rv32i_m/privilege/src/WALLY-periph-01.S", + "rv32i_m/privilege/src/WALLY-satp-invalid-01.S", + // These peripherals are here instead of wally32periph because they don't work on rv32imc, which lacks a PMP register to configure "rv32i_m/privilege/src/WALLY-gpio-01.S", "rv32i_m/privilege/src/WALLY-clint-01.S", "rv32i_m/privilege/src/WALLY-uart-01.S", "rv32i_m/privilege/src/WALLY-plic-01.S", "rv32i_m/privilege/src/WALLY-plic-s-01.S" + + }; + + string wally32periph[] = '{ + `WALLYTEST, + "rv32i_m/privilege/src/WALLY-periph-01.S" }; From 82ae3a74e22cddc1f1db6f4f94aad14b4fc9da97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 09:35:19 -0700 Subject: [PATCH 32/54] Fixed bitrot in testfloat tests --- testbench/testbench-fp.sv | 2 +- testbench/tests-fp.vh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 3359090ac..d1f6f9b63 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -702,7 +702,7 @@ module testbenchfp; if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), - .XZero(XZero), .XSubnorm(XSubnorm), .OpCtrl(OpCtrlVal), .IntZero, + .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); end diff --git a/testbench/tests-fp.vh b/testbench/tests-fp.vh index 1d4cfdc60..f72721a88 100644 --- a/testbench/tests-fp.vh +++ b/testbench/tests-fp.vh @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define PATH "../../tests/fp/vectors/" +`define PATH "../tests/fp/vectors/" `define ADD_OPCTRL 3'b110 `define MUL_OPCTRL 3'b100 `define SUB_OPCTRL 3'b111 From fd2d08f50187e61f12624353cdcc797c25d4ec8e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:21:33 -0700 Subject: [PATCH 33/54] Fixed fmv decoder --- src/fpu/fctrl.sv | 67 ++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index be10e8007..8428b8c75 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -75,16 +75,19 @@ module fctrl ( logic [1:0] FResSelD; // Select one of the results that finish in the memory stage logic [2:0] FrmD, FrmE; // FP rounding mode logic [`FMTBITS-1:0] FmtD; // FP format - logic [1:0] Fmt; // format - before possible reduction + logic [1:0] Fmt, Fmt2; // format - before possible reduction logic SupportedFmt; // is the format supported + logic SupportedFmt2; // is the source format supported for fp -> fp logic FCvtIntD, FCvtIntM; // convert to integer opperation // FPU Instruction Decoder assign Fmt = Funct7D[1:0]; + assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp - // Note: only Fmt is checked; fcvt does not check destination format assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) | (Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED)); + assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & `D_SUPPORTED) | + (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED)); // decode the instruction always_comb @@ -142,38 +145,42 @@ module fctrl ( default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass - else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w to int reg - else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d to int reg - else ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - 7'b1101000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s - 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s - 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s - 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s + ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass + else if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register + 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg + 7'b0100000: if (Rs2D[4:2] == 3'b000) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d + 7'b0100001: if (Rs2D[4:2] == 3'b000) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + // *** other formats here + /* verilator lint_off CASEINCOMPLETE */ + 7'b1101000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s endcase - 7'b1100000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w - 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu - 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l - 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu + 7'b1100000: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s s->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s s->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s s->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s s->lu endcase - 7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x to fp reg - 7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d - 7'b1101001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d - 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d - 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d - 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d + 7'b1101001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w w->d + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l l->d + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d endcase - 7'b1100001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w - 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu - 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l - 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu + 7'b1100001: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d d->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d d->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase - 7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.d.x to fp reg - 7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + /* verilator lint_off CASEINCOMPLETE */ default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction From e5955c5dd8d36cf98a6ea7345699e691fced6621 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:28:01 -0700 Subject: [PATCH 34/54] support more fp -> fp conversions --- src/fpu/fctrl.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 8428b8c75..5e7dd1aed 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -150,10 +150,14 @@ module fctrl ( ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg - 7'b0100000: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d - 7'b0100001: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) + 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h) + 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d) // *** other formats here /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D) From 40311c4f62b96edee2a9559911b8b7a3a7b0b435 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:35:41 -0700 Subject: [PATCH 35/54] fixed fp->fp conversions --- src/fpu/fctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5e7dd1aed..5a52b0484 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -155,9 +155,9 @@ module fctrl ( 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h) + ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d) + ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) // *** other formats here /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D) From f0cab709f28c4adbccaaf55f806f9defd9833d44 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:53:06 -0700 Subject: [PATCH 36/54] Added support (untested) for half and quad conversions --- src/fpu/fctrl.sv | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5a52b0484..a3e93ad7a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -184,6 +184,31 @@ module fctrl ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase + 7'b1101010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.h.l l->h + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.h.lu lu->h + endcase + 7'b1100010: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.h h->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.h h->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.h h->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.h h->lu + endcase + 7'b1101011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.q.w w->q + 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.q.wu wu->q + 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.q.l l->q + 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.q.lu lu->q + endcase + 7'b1100011: case(Rs2D) + 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.q q->w + 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu + 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l + 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu + endcase + /* verilator lint_off CASEINCOMPLETE */ default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase From 69f6b291c6385fa6d4a2b39b4a26f662881e04d2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 14:47:08 -0500 Subject: [PATCH 37/54] Possible fix for issue 148. I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works. --- src/cache/cachefsm.sv | 2 +- src/ebu/ahbcacheinterface.sv | 5 +++-- src/ebu/buscachefsm.sv | 5 +++-- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index c51257be7..cd1d43c55 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -135,7 +135,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( end // com back to CPU - assign CacheCommitted = CurrState != STATE_READY; + assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index b30a15096..e2e7d3696 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -33,7 +33,8 @@ module ahbcacheinterface #( parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline - parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter READ_ONLY_CACHE )( input logic HCLK, HRESETn, // bus interface controls @@ -115,7 +116,7 @@ module ahbcacheinterface #( flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index c619c9135..e0efcf3a3 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -33,7 +33,8 @@ // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index - parameter AHBWLOGBWPL // Log2 of BEATSPERLINE + parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE + parameter READ_ONLY_CACHE )( input logic HCLK, input logic HRESETn, @@ -121,7 +122,7 @@ module buscachefsm #( (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_WRITEBACK & ~HREADY); - assign BusCommitted = CurrState != ADR_PHASE; + assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3); // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) | diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 2a411a737..c1556daeb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -251,7 +251,7 @@ module ifu ( .NextSet(PCSpillNextF[11:0]), .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); - ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) + ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index e3adc00f5..0b0bc81e3 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -275,7 +275,7 @@ module lsu ( .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), From 7cc8d4f20cf670561b0422ad5316a6d580e33d0c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:09:54 -0500 Subject: [PATCH 38/54] Now have logging of i/d cache addresses, but the performance counter reports are x's. --- testbench/testbench.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f07cfef12..0afb4310b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -474,7 +474,7 @@ logic [3:0] dummy; // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) assign StartSampleFirst = InReset; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + flop #(1) StartSampleReg(clk, StartSampleFirst, StartSampleDelayed); assign StartSample = StartSampleFirst & ~ StartSampleDelayed; assign EndSample = DCacheFlushStart & ~DCacheFlushDone; @@ -555,16 +555,19 @@ end int file; string LogFile; logic resetD, resetEdge; + logic Enable; + assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin LogFile = $psprintf("ICache.log"); file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(~dut.core.StallD & ~dut.core.FlushD) begin + if(Enable) begin // only log i cache reads $fwrite(file, "%h R\n", dut.core.ifu.PCPF); end if(EndSample) $fwrite(file, "END %s\n", memfilename); @@ -580,6 +583,7 @@ end initial begin LogFile = $psprintf("DCache.log"); file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); From a48049f6fe9832f297fa28f4e3769c054097c4e0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:15:05 -0500 Subject: [PATCH 39/54] Restored performance counter reports. --- testbench/testbench.sv | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0afb4310b..1af6f2b13 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -169,7 +169,8 @@ logic [3:0] dummy; logic InitializingMemories; integer ResetCount, ResetThreshold; logic InReset; - + logic Begin; + // instantiate device to be tested assign GPIOIN = 0; assign UARTSin = 1; @@ -417,7 +418,7 @@ logic [3:0] dummy; if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; - logic StartSampleDelayed; + logic StartSampleDelayed, BeginDelayed; logic EndSampleFirst, EndSampleDelayed; logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; @@ -474,10 +475,13 @@ logic [3:0] dummy; // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) assign StartSampleFirst = InReset; - flop #(1) StartSampleReg(clk, StartSampleFirst, StartSampleDelayed); + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; + + flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); + assign Begin = StartSampleFirst & ~ BeginDelayed; + end always @(negedge clk) begin @@ -566,7 +570,7 @@ end end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(Enable) begin // only log i cache reads $fwrite(file, "%h R\n", dut.core.ifu.PCPF); end @@ -587,7 +591,7 @@ end end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); From cef75cfe06caaf63878698d6c5168c07745c0c45 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:20:14 -0500 Subject: [PATCH 40/54] Now reports if there is a hit or miss. --- testbench/testbench.sv | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1af6f2b13..aa11d377c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -568,11 +568,13 @@ end file = $fopen(LogFile, "w"); $fwrite(file, "BEGIN %s\n", memfilename); end + string HitMissString; + assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : "M"; always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(Enable) begin // only log i cache reads - $fwrite(file, "%h R\n", dut.core.ifu.PCPF); + $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); end if(EndSample) $fwrite(file, "END %s\n", memfilename); end @@ -582,8 +584,10 @@ end int file; string LogFile; logic resetD, resetEdge; + string HitMissString; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; + assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : "M"; initial begin LogFile = $psprintf("DCache.log"); file = $fopen(LogFile, "w"); @@ -594,13 +598,13 @@ end if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin - $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h R %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin - $fwrite(file, "%h W\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h W %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change - $fwrite(file, "%h A\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h A %s\n", dut.core.lsu.PAdrM, HitMissString); end else if (dut.core.lsu.bus.dcache.FlushDCache) begin - $fwrite(file, "%h F\n", dut.core.lsu.PAdrM); + $fwrite(file, "%h F %s\n", dut.core.lsu.PAdrM, HitMissString); end end if(EndSample) $fwrite(file, "END %s\n", memfilename); From 34dd2850e09d4fb04d52c9483532ecf1070326ee Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:20:45 -0500 Subject: [PATCH 41/54] Disable loggers by default. --- testbench/testbench.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index aa11d377c..cc0f0a241 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -29,9 +29,9 @@ `include "tests.vh" `define PrintHPMCounters 1 -`define BPRED_LOGGER 1 -`define I_CACHE_ADDR_LOGGER 1 -`define D_CACHE_ADDR_LOGGER 1 +`define BPRED_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 0 +`define D_CACHE_ADDR_LOGGER 0 module testbench; parameter DEBUG=0; From b4338a5a50126af83c583652a678be3c6d71dda9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Mar 2023 16:27:54 -0500 Subject: [PATCH 42/54] Modified the testbench to not use the loggers for unsupported configurations. --- testbench/testbench.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index cc0f0a241..4372fd4e5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -532,7 +532,7 @@ logic [3:0] dummy; // initialize the branch predictor - if (`BPRED_SUPPORTED == 1) begin + if (`BPRED_SUPPORTED) begin integer adrindex; always @(*) begin @@ -555,7 +555,7 @@ logic [3:0] dummy; end - if (`I_CACHE_ADDR_LOGGER == 1) begin + if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin int file; string LogFile; logic resetD, resetEdge; @@ -580,7 +580,7 @@ end end end - if (`D_CACHE_ADDR_LOGGER == 1) begin + if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin int file; string LogFile; logic resetD, resetEdge; @@ -611,7 +611,7 @@ end end end - if (`BPRED_SUPPORTED == 1) begin + if (`BPRED_SUPPORTED) begin if (`BPRED_LOGGER) begin string direction; int file; From bfb4f0d6eba72cdee8c209b3f13123028651df26 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Thu, 23 Mar 2023 21:39:42 +0000 Subject: [PATCH 43/54] add check for legal funct3 for IW instructions --- src/ieu/controller.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index da99a48f6..5d0b78457 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -131,6 +131,7 @@ module controller( logic JFunctD; // detect jalr instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control + logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions // Extract fields assign OpD = InstrD[6:0]; @@ -161,6 +162,7 @@ module controller( ((`XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches assign JFunctD = (Funct3D == 3'b000); + assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101; end else begin:legalcheck2 assign IFunctD = 1; // Don't bother to separate out shift decoding assign RFunctD = ~Funct7D[0]; // Not a multiply @@ -168,7 +170,8 @@ module controller( assign LFunctD = 1; // don't bother to check Funct3 for loads assign SFunctD = 1; // don't bother to check Funct3 for stores assign BFunctD = 1; // don't bother to check Funct3 for branches - assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign IWValidFunct3D = 1; end // Main Instruction Decoder @@ -187,7 +190,7 @@ module controller( 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc - 7'b0011011: if (IFunctD & `XLEN == 64) + 7'b0011011: if (IFunctD & IWValidFunct3D & `XLEN == 64) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores From 7132271a83f0349e44128fe2b88057ebfa1c249f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:13:25 -0700 Subject: [PATCH 44/54] Started adding fpu fctrl tests --- testbench/tests.vh | 1 + tests/coverage/Makefile | 2 +- tests/coverage/fpu.S | 69 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 tests/coverage/fpu.S diff --git a/testbench/tests.vh b/testbench/tests.vh index 79f100d4f..fab26208a 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -47,6 +47,7 @@ string tvpaths[] = '{ "ieu", "ebu", "csrwrites", + "fpu", "priv" }; diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 7d4552af2..b2a2544d3 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,7 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc_zba_zbb_zbc_zbs -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S new file mode 100644 index 000000000..34924a40a --- /dev/null +++ b/tests/coverage/fpu.S @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// fpu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for FPU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + # Test legal instructions not covered elsewhere + flq ft0, 0(a0) + flh ft0, 8(a0) + fsq ft0, 0(a0) + fsh ft0, 8(a0) + fcvt.h.s ft1, ft0 + fcvt.q.s ft2, ft0 + fcvt.h.w ft3, a0 + fcvt.h.wu ft3, a0 + fcvt.h.l ft3, a0 + fcvt.h.lu ft3, a0 + fcvt.w.h a0, ft3 + fcvt.wu.h a0, ft3 + fcvt.l.h a0, ft3 + fcvt.lu.h a0, ft3 + fcvt.q.w ft3, a0 + fcvt.q.wu ft3, a0 + fcvt.q.l ft3, a0 + fcvt.q.lu ft3, a0 + fcvt.w.q a0, ft3 + fcvt.wu.q a0, ft3 + fcvt.l.q a0, ft3 + fcvt.lu.q a0, ft3 + + + # Test illegal instructions are detected + .word 0x00000007 // illegal floating-point load (bad Funct3) + .word 0x00000027 // illegal floating-point store (bad Funct3) + .word 0x58F00053 // illegal fsqrt (bad Rs2D) + .word 0x20007053 // illegal fsgnj (bad Funct3) + .word 0x28007053 // illegal fmin/max (bad Funct3) + .word 0xA0007053 // illegal fcmp (bad Funct3) + .word 0xE0007053 // illegal fclass/fmv (bad Funct3) + .word 0xF0007053 // illegal fmv (bad Funct3) + .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) + .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + + j done + From 043e4fe5f4bc4e272e22b44fba61ebb2f8721000 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:13:48 -0700 Subject: [PATCH 45/54] Simplified fctrl --- src/fpu/fctrl.sv | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index a3e93ad7a..ad9007014 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -90,32 +90,27 @@ module fctrl ( (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED)); // decode the instruction - always_comb + // ControlsD: FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt + always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format - else case(OpD) - // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt + else begin + ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // default: illegal FPU instruction + /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed + case(OpD) 7'b0000111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b0100111: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh - else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub @@ -131,18 +126,15 @@ module fctrl ( 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - endcase + endcase 7'b00101??: case(Funct3D) 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction endcase 7'b10100??: case(Funct3D) 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass @@ -158,9 +150,7 @@ module fctrl ( ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - // *** other formats here - /* verilator lint_off CASEINCOMPLETE */ - 7'b1101000: case(Rs2D) + 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s @@ -207,13 +197,11 @@ module fctrl ( 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu - endcase - - /* verilator lint_off CASEINCOMPLETE */ - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction + endcase endcase - default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction - endcase + endcase + /* verilator lint_off CASEINCOMPLETE */ + end // unswizzle control bits assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD; From 4c41589329ef2161c15fcfbb4275dd3f8c50ff22 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 21:28:56 -0700 Subject: [PATCH 46/54] Turned off hpm counters --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4372fd4e5..2bc3622c1 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 1 +`define PrintHPMCounters 0 `define BPRED_LOGGER 0 `define I_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 0 From 0e0237853275eceebadb55d55816db3c4aa071ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Mar 2023 06:10:05 -0700 Subject: [PATCH 47/54] Turned on FS bit in fpu.S coverage test --- tests/coverage/fpu.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 34924a40a..1a2d5ce7b 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -28,6 +28,9 @@ main: + bseti t0, zero, 14 # turn on FPU + csrs mstatus, t0 + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) From de2a0da9e93b903b1cfc95733b26cb3b5286d574 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Mar 2023 07:02:09 -0700 Subject: [PATCH 48/54] Reduced number of bits in mcause and medeleg registers --- src/privileged/csr.sv | 11 ++++++----- src/privileged/csrm.sv | 21 +++++++++++---------- src/privileged/csrs.sv | 9 +++++---- src/privileged/privileged.sv | 4 ++-- src/privileged/trap.sv | 8 ++++---- 5 files changed, 28 insertions(+), 25 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 1478b5fc0..f44785287 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -55,7 +55,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode input logic [1:0] PrivilegeModeW, // current privilege mode - input logic [`LOG_XLEN-1:0] CauseM, // Trap cause + input logic [3:0] CauseM, // Trap cause input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode // inputs for performance counters input logic LoadStallD, @@ -79,7 +79,7 @@ module csr #(parameter // outputs from CSRs output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, - output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [15:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, @@ -107,7 +107,8 @@ module csr #(parameter logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic WriteFRMM, WriteFFLAGSM; - logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; + logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM; + logic [4:0] NextCauseM; logic [11:0] CSRAdrM; logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM; logic InsufficientCSRPrivilegeM; @@ -153,7 +154,7 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; // 64-byte alignment allows concatenation rather than addition + assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; @@ -196,7 +197,7 @@ module csr #(parameter assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment - assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM; + assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index daf7e1012..9f00f3a68 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -69,20 +69,21 @@ module csrm #(parameter DSCRATCH1 = 12'h7B3, // Constants ZERO = {(`XLEN){1'b0}}, - MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11), + MEDELEG_MASK = 16'hB3FF, MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable ) ( input logic clk, reset, input logic InstrValidNotFlushedM, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, + input logic [`XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, + input logic [4:0] NextCauseM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] MIP_REGW, MIE_REGW, output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, output logic [`XLEN-1:0] MEPC_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, - output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [15:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], @@ -91,8 +92,8 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW; - logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW; + logic [4:0] MCAUSE_REGW; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; @@ -150,13 +151,13 @@ module csrm #(parameter // CSRs flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); if (`S_SUPPORTED) begin:deleg // DELEG registers should exist - flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, MEDELEG_REGW); - flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); + flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW); + flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); - flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); + flopenr #(5) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); @@ -192,13 +193,13 @@ module csrm #(parameter MSTATUS: CSRMReadValM = MSTATUS_REGW; MSTATUSH: CSRMReadValM = MSTATUSH_REGW; MTVEC: CSRMReadValM = MTVEC_REGW; - MEDELEG: CSRMReadValM = MEDELEG_REGW; + MEDELEG: CSRMReadValM = {{(`XLEN-16){1'b0}}, MEDELEG_REGW}; MIDELEG: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW}; MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW}; MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; MEPC: CSRMReadValM = MEPC_REGW; - MCAUSE: CSRMReadValM = MCAUSE_REGW; + MCAUSE: CSRMReadValM = {MCAUSE_REGW[4], {(`XLEN-5){1'b0}}, MCAUSE_REGW[3:0]}; MTVAL: CSRMReadValM = MTVAL_REGW; MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW}; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 3d75ef73e..598eed155 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -48,7 +48,8 @@ module csrs #(parameter input logic InstrValidNotFlushedM, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, + input logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, + input logic [4:0] NextCauseM, input logic STATUS_TVM, input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear input logic [`XLEN-1:0] CSRWriteValM, @@ -73,7 +74,7 @@ module csrs #(parameter logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - logic [`XLEN-1:0] SCAUSE_REGW; + logic [4:0] SCAUSE_REGW; logic [63:0] STIMECMP_REGW; // write enables @@ -93,7 +94,7 @@ module csrs #(parameter flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); + flopenr #(5) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); if (`VIRTMEM_SUPPORTED) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); @@ -126,7 +127,7 @@ module csrs #(parameter SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; - SCAUSE: CSRSReadValM = SCAUSE_REGW; + SCAUSE: CSRSReadValM = {SCAUSE_REGW[4], {(`XLEN-5){1'b0}}, SCAUSE_REGW[3:0]}; STVAL: CSRSReadValM = STVAL_REGW; SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 1975db10e..6fa8dcf98 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -96,8 +96,8 @@ module privileged ( output logic WFIStallM // Stall in Memory stage for WFI until interrupt or timeout ); - logic [`LOG_XLEN-1:0] CauseM; // trap cause - logic [`XLEN-1:0] MEDELEG_REGW; // exception delegation CSR + logic [3:0] CauseM; // trap cause + logic [15:0] MEDELEG_REGW; // exception delegation CSR logic [11:0] MIDELEG_REGW; // interrupt delegation CSR logic sretM, mretM; // supervisor / machine return instruction logic IllegalCSRAccessM; // Illegal access to CSR diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index d50b5fb48..ace63b48b 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -38,7 +38,7 @@ module trap ( input logic wfiM, // wait for interrupt instruction input logic [1:0] PrivilegeModeW, // current privilege mode input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs - input logic [`XLEN-1:0] MEDELEG_REGW, // exception delegation SR + input logic [15:0] MEDELEG_REGW, // exception delegation SR input logic STATUS_MIE, STATUS_SIE, // machine/supervisor interrupt enables input logic InstrValidM, // current instruction is valid, not flushed input logic CommittedM, CommittedF, // LSU/IFU has committed to a bus operation that can't be interrupted @@ -49,7 +49,7 @@ module trap ( output logic IntPendingM, // Interrupt is pending, might occur if enabled output logic DelegateM, // Delegate trap to supervisor handler output logic WFIStallM, // Stall due to WFI instruction - output logic [`LOG_XLEN-1:0] CauseM // trap cause + output logic [3:0] CauseM // trap cause ); logic MIntGlobalEnM, SIntGlobalEnM; // Global interupt enables @@ -72,7 +72,7 @@ module trap ( assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); assign ValidIntsM = {12{~Committed}} & EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. - assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & + assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); assign WFIStallM = wfiM & ~IntPendingM; @@ -109,7 +109,7 @@ module trap ( else if (IllegalInstrFaultM) CauseM = 2; else if (InstrMisalignedFaultM) CauseM = 0; else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; + else if (EcallFaultM) CauseM = {2'b10, PrivilegeModeW}; else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; else if (LoadPageFaultM) CauseM = 13; From da905b4eb97cfe5989a18721cd8ffe9e8149566a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 15:04:56 -0700 Subject: [PATCH 49/54] Resolved ImperasDV receiving incorrect cause values --- src/privileged/csrm.sv | 8 ++++---- src/privileged/csrs.sv | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 9f00f3a68..1511732f7 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -92,8 +92,8 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW; - logic [4:0] MCAUSE_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; + // logic [4:0] ; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; @@ -157,7 +157,7 @@ module csrm #(parameter flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); - flopenr #(5) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); + flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW); if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); @@ -199,7 +199,7 @@ module csrm #(parameter MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; MEPC: CSRMReadValM = MEPC_REGW; - MCAUSE: CSRMReadValM = {MCAUSE_REGW[4], {(`XLEN-5){1'b0}}, MCAUSE_REGW[3:0]}; + MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW}; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 598eed155..f14cc30ff 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -73,8 +73,8 @@ module csrs #(parameter logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; - logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - logic [4:0] SCAUSE_REGW; + logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; + // logic [4:0] ; logic [63:0] STIMECMP_REGW; // write enables @@ -94,7 +94,7 @@ module csrs #(parameter flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenr #(5) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); + flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); if (`VIRTMEM_SUPPORTED) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); @@ -127,7 +127,7 @@ module csrs #(parameter SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; - SCAUSE: CSRSReadValM = {SCAUSE_REGW[4], {(`XLEN-5){1'b0}}, SCAUSE_REGW[3:0]}; + SCAUSE: CSRSReadValM = SCAUSE_REGW; STVAL: CSRSReadValM = STVAL_REGW; SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin From ede13491efc65d10109117e67bde45ac5ecc1bb9 Mon Sep 17 00:00:00 2001 From: Sydney Riley Date: Wed, 29 Mar 2023 15:15:47 -0700 Subject: [PATCH 50/54] Starting IFU tests including c.fld compressed instruction --- testbench/tests.vh | 3 ++- tests/coverage/ifu.S | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 tests/coverage/ifu.S diff --git a/testbench/tests.vh b/testbench/tests.vh index 79f100d4f..e03d50e30 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -47,7 +47,8 @@ string tvpaths[] = '{ "ieu", "ebu", "csrwrites", - "priv" + "priv", + "ifu" }; string coremark[] = '{ diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S new file mode 100644 index 000000000..a3a5e7d29 --- /dev/null +++ b/tests/coverage/ifu.S @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ifu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + # turn floating point on + li t0, 0x2000 + csrs mstatus, t0 + + # calling compressed floating point load double instruction + //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + // binary version 0000 0000 0000 0000 0010 0000 0000 0000 + mv s0, sp + c.fld fs0, 0(s0) + + j done From 287df517b9c363e6c15c798f48bae837a68aebb7 Mon Sep 17 00:00:00 2001 From: Sydney Riley Date: Wed, 29 Mar 2023 15:20:46 -0700 Subject: [PATCH 51/54] Corrected authorship for IFU.S tests file --- tests/coverage/ifu.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index a3a5e7d29..3ceeeac12 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ifu.S // -// Written: David_Harris@hmc.edu 28 March 2023 +// Written: sriley@g.hmc.edu 28 March 2023 // // Purpose: Test coverage for IFU // From 414cd26a9df6afe11b2565dbec0276a8cc98792a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 15:24:00 -0700 Subject: [PATCH 52/54] updated tests to reflect non-writeable bits of deleg --- .../privilege/references/WALLY-trap-01.reference_output | 4 ++-- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ++-- .../privilege/references/WALLY-trap-u-01.reference_output | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 78e096cee..39ec3ad42 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -108,8 +108,8 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index dc5acb4d6..4c3031eb2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -98,8 +98,8 @@ 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 0000000b # scause from M mode ecall diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 7afec5268..2d1d16d27 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -92,8 +92,8 @@ 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -ffffffff +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 0000000b # scause from M mode ecall From 7881c245a22e02142c38e8988e764522e7566d10 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 16:31:28 -0700 Subject: [PATCH 53/54] ported medelg fixes to 32 bit tests. Requires a make allclean --- .../rv32i_m/privilege/references/WALLY-trap-01.reference_output | 2 +- .../privilege/references/WALLY-trap-s-01.reference_output | 2 +- .../privilege/references/WALLY-trap-u-01.reference_output | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index a9c3da2c0..fb24280ad 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -53,7 +53,7 @@ 8000000b # mcause value from m ext interrupt 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index e57184719..9dbdd8337 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -48,7 +48,7 @@ 00000009 # scause from S mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 5c6d8378d..b19a0c21e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -45,7 +45,7 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 -fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) From 94f03b0d785f70e763205ba4928a49a21d241319 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 29 Mar 2023 19:32:57 -0700 Subject: [PATCH 54/54] unnecessary comments cleanup --- src/privileged/csrm.sv | 1 - src/privileged/csrs.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 1511732f7..e8a42773d 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -93,7 +93,6 @@ module csrm #(parameter logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; - // logic [4:0] ; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index f14cc30ff..f6d02fe14 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -74,7 +74,6 @@ module csrs #(parameter logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSTIMECMPM, WriteSTIMECMPHM; logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; - // logic [4:0] ; logic [63:0] STIMECMP_REGW; // write enables