diff --git a/wallyVirtIO.patch b/wallyVirtIO.patch new file mode 100644 index 000000000..76a1d240e --- /dev/null +++ b/wallyVirtIO.patch @@ -0,0 +1,542 @@ +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index 4a3cd2599a..39b46e3122 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -20,6 +20,7 @@ + + #include "qemu/osdep.h" + #include "qemu/units.h" ++#include "qemu/log.h" + #include "qemu/error-report.h" + #include "qapi/error.h" + #include "hw/boards.h" +@@ -44,19 +45,10 @@ + #include "hw/display/ramfb.h" + + static const MemMapEntry virt_memmap[] = { +- [VIRT_DEBUG] = { 0x0, 0x100 }, + [VIRT_MROM] = { 0x1000, 0xf000 }, +- [VIRT_TEST] = { 0x100000, 0x1000 }, +- [VIRT_RTC] = { 0x101000, 0x1000 }, + [VIRT_CLINT] = { 0x2000000, 0x10000 }, +- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, + [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, + [VIRT_UART0] = { 0x10000000, 0x100 }, +- [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, +- [VIRT_FW_CFG] = { 0x10100000, 0x18 }, +- [VIRT_FLASH] = { 0x20000000, 0x4000000 }, +- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, +- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, + [VIRT_DRAM] = { 0x80000000, 0x0 }, + }; + +@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = { + /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ + #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) + +-static MemMapEntry virt_high_pcie_memmap; +- + #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) + +-static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, +- const char *name, +- const char *alias_prop_name) +-{ +- /* +- * Create a single flash device. We use the same parameters as +- * the flash devices on the ARM virt board. +- */ +- DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); +- +- qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); +- qdev_prop_set_uint8(dev, "width", 4); +- qdev_prop_set_uint8(dev, "device-width", 2); +- qdev_prop_set_bit(dev, "big-endian", false); +- qdev_prop_set_uint16(dev, "id0", 0x89); +- qdev_prop_set_uint16(dev, "id1", 0x18); +- qdev_prop_set_uint16(dev, "id2", 0x00); +- qdev_prop_set_uint16(dev, "id3", 0x00); +- qdev_prop_set_string(dev, "name", name); +- +- object_property_add_child(OBJECT(s), name, OBJECT(dev)); +- object_property_add_alias(OBJECT(s), alias_prop_name, +- OBJECT(dev), "drive"); +- +- return PFLASH_CFI01(dev); +-} +- +-static void virt_flash_create(RISCVVirtState *s) +-{ +- s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); +- s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); +-} +- +-static void virt_flash_map1(PFlashCFI01 *flash, +- hwaddr base, hwaddr size, +- MemoryRegion *sysmem) +-{ +- DeviceState *dev = DEVICE(flash); +- +- assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); +- assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); +- qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); +- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); +- +- memory_region_add_subregion(sysmem, base, +- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), +- 0)); +-} +- +-static void virt_flash_map(RISCVVirtState *s, +- MemoryRegion *sysmem) +-{ +- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; +- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; +- +- virt_flash_map1(s->flash[0], flashbase, flashsize, +- sysmem); +- virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, +- sysmem); +-} +- +-static void create_pcie_irq_map(void *fdt, char *nodename, +- uint32_t plic_phandle) +-{ +- int pin, dev; +- uint32_t +- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; +- uint32_t *irq_map = full_irq_map; +- +- /* This code creates a standard swizzle of interrupts such that +- * each device's first interrupt is based on it's PCI_SLOT number. +- * (See pci_swizzle_map_irq_fn()) +- * +- * We only need one entry per interrupt in the table (not one per +- * possible slot) seeing the interrupt-map-mask will allow the table +- * to wrap to any number of devices. +- */ +- for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { +- int devfn = dev * 0x8; +- +- for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { +- int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); +- int i = 0; +- +- irq_map[i] = cpu_to_be32(devfn << 8); +- +- i += FDT_PCI_ADDR_CELLS; +- irq_map[i] = cpu_to_be32(pin + 1); +- +- i += FDT_PCI_INT_CELLS; +- irq_map[i++] = cpu_to_be32(plic_phandle); +- +- i += FDT_PLIC_ADDR_CELLS; +- irq_map[i] = cpu_to_be32(irq_nr); +- +- irq_map += FDT_INT_MAP_WIDTH; +- } +- } +- +- qemu_fdt_setprop(fdt, nodename, "interrupt-map", +- full_irq_map, sizeof(full_irq_map)); +- +- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", +- 0x1800, 0, 0, 0x7); +-} +- + static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, + uint64_t mem_size, const char *cmdline, bool is_32_bit) + { + void *fdt; +- int i, cpu, socket; ++ //int i, cpu, socket; ++ int cpu, socket; + MachineState *mc = MACHINE(s); + uint64_t addr, size; + uint32_t *clint_cells, *plic_cells; + unsigned long clint_addr, plic_addr; + uint32_t plic_phandle[MAX_NODES]; +- uint32_t cpu_phandle, intc_phandle, test_phandle; ++ uint32_t cpu_phandle, intc_phandle; + uint32_t phandle = 1, plic_mmio_phandle = 1; +- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; + char *mem_name, *cpu_name, *core_name, *intc_name; + char *name, *clint_name, *plic_name, *clust_name; +- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; +- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; +- static const char * const clint_compat[2] = { +- "sifive,clint0", "riscv,clint0" +- }; +- static const char * const plic_compat[2] = { +- "sifive,plic-1.0.0", "riscv,plic0" +- }; + + if (mc->dtb) { + fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); +@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, + (memmap[VIRT_CLINT].size * socket); + clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); + qemu_fdt_add_subnode(fdt, clint_name); +- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", +- (char **)&clint_compat, ARRAY_SIZE(clint_compat)); ++ qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); + qemu_fdt_setprop_cells(fdt, clint_name, "reg", + 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", +@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, + "#address-cells", FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, plic_name, + "#interrupt-cells", FDT_PLIC_INT_CELLS); +- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", +- (char **)&plic_compat, ARRAY_SIZE(plic_compat)); ++ qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); + qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", + plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); +@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, + for (socket = 0; socket < riscv_socket_count(mc); socket++) { + if (socket == 0) { + plic_mmio_phandle = plic_phandle[socket]; +- plic_virtio_phandle = plic_phandle[socket]; +- plic_pcie_phandle = plic_phandle[socket]; +- } +- if (socket == 1) { +- plic_virtio_phandle = plic_phandle[socket]; +- plic_pcie_phandle = plic_phandle[socket]; +- } +- if (socket == 2) { +- plic_pcie_phandle = plic_phandle[socket]; + } + } + + riscv_socket_fdt_write_distance_matrix(mc, fdt); + +- for (i = 0; i < VIRTIO_COUNT; i++) { +- name = g_strdup_printf("/soc/virtio_mmio@%lx", +- (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); +- qemu_fdt_add_subnode(fdt, name); +- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); +- qemu_fdt_setprop_cells(fdt, name, "reg", +- 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, +- 0x0, memmap[VIRT_VIRTIO].size); +- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", +- plic_virtio_phandle); +- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); +- g_free(name); +- } +- +- name = g_strdup_printf("/soc/pci@%lx", +- (long) memmap[VIRT_PCIE_ECAM].base); +- qemu_fdt_add_subnode(fdt, name); +- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); +- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); +- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); +- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); +- qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); +- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); +- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, +- memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); +- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); +- qemu_fdt_setprop_cells(fdt, name, "reg", 0, +- memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); +- qemu_fdt_setprop_sized_cells(fdt, name, "ranges", +- 1, FDT_PCI_RANGE_IOPORT, 2, 0, +- 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, +- 1, FDT_PCI_RANGE_MMIO, +- 2, memmap[VIRT_PCIE_MMIO].base, +- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, +- 1, FDT_PCI_RANGE_MMIO_64BIT, +- 2, virt_high_pcie_memmap.base, +- 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); +- +- create_pcie_irq_map(fdt, name, plic_pcie_phandle); +- g_free(name); +- +- test_phandle = phandle++; +- name = g_strdup_printf("/soc/test@%lx", +- (long)memmap[VIRT_TEST].base); +- qemu_fdt_add_subnode(fdt, name); +- { +- static const char * const compat[3] = { +- "sifive,test1", "sifive,test0", "syscon" +- }; +- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, +- ARRAY_SIZE(compat)); +- } +- qemu_fdt_setprop_cells(fdt, name, "reg", +- 0x0, memmap[VIRT_TEST].base, +- 0x0, memmap[VIRT_TEST].size); +- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); +- test_phandle = qemu_fdt_get_phandle(fdt, name); +- g_free(name); +- +- name = g_strdup_printf("/soc/reboot"); +- qemu_fdt_add_subnode(fdt, name); +- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); +- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); +- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); +- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); +- g_free(name); +- +- name = g_strdup_printf("/soc/poweroff"); +- qemu_fdt_add_subnode(fdt, name); +- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); +- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); +- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); +- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); +- g_free(name); +- + name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); +@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); + g_free(name); + +- name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); +- qemu_fdt_add_subnode(fdt, name); +- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); +- qemu_fdt_setprop_cells(fdt, name, "reg", +- 0x0, memmap[VIRT_RTC].base, +- 0x0, memmap[VIRT_RTC].size); +- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); +- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); +- g_free(name); +- +- name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); +- qemu_fdt_add_subnode(mc->fdt, name); +- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); +- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", +- 2, flashbase, 2, flashsize, +- 2, flashbase + flashsize, 2, flashsize); +- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); +- g_free(name); +- + update_bootargs: + if (cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); + } + } + +-static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, +- hwaddr ecam_base, hwaddr ecam_size, +- hwaddr mmio_base, hwaddr mmio_size, +- hwaddr high_mmio_base, +- hwaddr high_mmio_size, +- hwaddr pio_base, +- DeviceState *plic) +-{ +- DeviceState *dev; +- MemoryRegion *ecam_alias, *ecam_reg; +- MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; +- qemu_irq irq; +- int i; +- +- dev = qdev_new(TYPE_GPEX_HOST); +- +- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); +- +- ecam_alias = g_new0(MemoryRegion, 1); +- ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); +- memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", +- ecam_reg, 0, ecam_size); +- memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); +- +- mmio_alias = g_new0(MemoryRegion, 1); +- mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); +- memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", +- mmio_reg, mmio_base, mmio_size); +- memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); +- +- /* Map high MMIO space */ +- high_mmio_alias = g_new0(MemoryRegion, 1); +- memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", +- mmio_reg, high_mmio_base, high_mmio_size); +- memory_region_add_subregion(get_system_memory(), high_mmio_base, +- high_mmio_alias); +- +- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); +- +- for (i = 0; i < GPEX_NUM_IRQS; i++) { +- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); +- +- sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); +- gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); +- } +- +- return dev; +-} +- +-static FWCfgState *create_fw_cfg(const MachineState *mc) +-{ +- hwaddr base = virt_memmap[VIRT_FW_CFG].base; +- hwaddr size = virt_memmap[VIRT_FW_CFG].size; +- FWCfgState *fw_cfg; +- char *nodename; +- +- fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, +- &address_space_memory); +- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); +- +- nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); +- qemu_fdt_add_subnode(mc->fdt, nodename); +- qemu_fdt_setprop_string(mc->fdt, nodename, +- "compatible", "qemu,fw-cfg-mmio"); +- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", +- 2, base, 2, size); +- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); +- g_free(nodename); +- return fw_cfg; +-} +- + static void virt_machine_init(MachineState *machine) + { + const MemMapEntry *memmap = virt_memmap; +@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine) + target_ulong firmware_end_addr, kernel_start_addr; + uint32_t fdt_load_addr; + uint64_t kernel_entry; +- DeviceState *mmio_plic, *virtio_plic, *pcie_plic; ++ DeviceState *mmio_plic; + int i, j, base_hartid, hart_count; + + /* Check socket count limit */ +@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine) + } + + /* Initialize sockets */ +- mmio_plic = virtio_plic = pcie_plic = NULL; ++ mmio_plic = NULL; + for (i = 0; i < riscv_socket_count(machine); i++) { + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); +@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine) + /* Try to use different PLIC instance based device type */ + if (i == 0) { + mmio_plic = s->plic[i]; +- virtio_plic = s->plic[i]; +- pcie_plic = s->plic[i]; +- } +- if (i == 1) { +- virtio_plic = s->plic[i]; +- pcie_plic = s->plic[i]; +- } +- if (i == 2) { +- pcie_plic = s->plic[i]; + } + } + +@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine) + error_report("Limiting RAM size to 10 GiB"); + } + #endif +- virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; +- virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; +- } else { +- virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; +- virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; +- virt_high_pcie_memmap.base = +- ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); + } + + /* register system main memory (actual RAM) */ +@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine) + + if (riscv_is_32bit(&s->soc[0])) { + firmware_end_addr = riscv_find_and_load_firmware(machine, +- RISCV32_BIOS_BIN, start_addr, NULL); ++ "opensbi-riscv32-generic-fw_dynamic.bin", ++ start_addr, NULL); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, +- RISCV64_BIOS_BIN, start_addr, NULL); ++ "opensbi-riscv64-generic-fw_dynamic.bin", ++ start_addr, NULL); + } + + if (machine->kernel_filename) { +@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine) + kernel_entry = 0; + } + +- if (drive_get(IF_PFLASH, 0, 0)) { +- /* +- * Pflash was supplied, let's overwrite the address we jump to after +- * reset to the base of the flash. +- */ +- start_addr = virt_memmap[VIRT_FLASH].base; +- } +- +- /* +- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device +- * tree cannot be altered and we get FDT_ERR_NOSPACE. +- */ +- s->fw_cfg = create_fw_cfg(machine); +- rom_set_fw(s->fw_cfg); +- + /* Compute the fdt load address in dram */ + fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, + machine->ram_size, machine->fdt); +@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine) + virt_memmap[VIRT_MROM].size, kernel_entry, + fdt_load_addr, machine->fdt); + +- /* SiFive Test MMIO device */ +- sifive_test_create(memmap[VIRT_TEST].base); +- +- /* VirtIO MMIO devices */ +- for (i = 0; i < VIRTIO_COUNT; i++) { +- sysbus_create_simple("virtio-mmio", +- memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, +- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); +- } +- +- gpex_pcie_init(system_memory, +- memmap[VIRT_PCIE_ECAM].base, +- memmap[VIRT_PCIE_ECAM].size, +- memmap[VIRT_PCIE_MMIO].base, +- memmap[VIRT_PCIE_MMIO].size, +- virt_high_pcie_memmap.base, +- virt_high_pcie_memmap.size, +- memmap[VIRT_PCIE_PIO].base, +- DEVICE(pcie_plic)); +- +- serial_mm_init(system_memory, memmap[VIRT_UART0].base, ++ serial_mm_init(system_memory, memmap[VIRT_UART0].base, + 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, + serial_hd(0), DEVICE_LITTLE_ENDIAN); + +- sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, +- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); +- +- virt_flash_create(s); +- +- for (i = 0; i < ARRAY_SIZE(s->flash); i++) { +- /* Map legacy -drive if=pflash to machine properties */ +- pflash_cfi01_legacy_drive(s->flash[i], +- drive_get(IF_PFLASH, 0, i)); +- } +- virt_flash_map(s, system_memory); + } + + static void virt_machine_instance_init(Object *obj) +diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c +index 991a6bb760..401028b8d9 100644 +--- a/target/riscv/cpu.c ++++ b/target/riscv/cpu.c +@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); ++ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); ++ + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); + }