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Cleaned up some names in dcache and lsu.

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This commit is contained in:
Ross Thompson 2021-12-29 11:21:44 -06:00
parent fe22d4544f
commit bc437cf7e0
4 changed files with 152 additions and 194 deletions
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70
wally-pipelined/src/cache/dcache.sv vendored
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@ -44,10 +44,10 @@ module dcache
output logic DCacheStall, output logic DCacheStall,
output logic DCacheMiss, output logic DCacheMiss,
output logic DCacheAccess, output logic DCacheAccess,
output logic DCCommittedM, output logic DCacheCommittedM,
output logic DCWriteLine, output logic DCacheWriteLine,
output logic DCFetchLine, output logic DCacheFetchLine,
input logic BUSACK, input logic DCacheBusAck,
output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`PA_BITS-1:0] DCacheBusAdr,
@ -80,7 +80,6 @@ module dcache
logic [1:0] SelAdrM; logic [1:0] SelAdrM;
logic [INDEXLEN-1:0] RAdr; logic [INDEXLEN-1:0] RAdr;
logic [INDEXLEN-1:0] WAdr;
logic [BLOCKLEN-1:0] SRAMWriteData; logic [BLOCKLEN-1:0] SRAMWriteData;
logic SetValid, ClearValid; logic SetValid, ClearValid;
logic SetDirty, ClearDirty; logic SetDirty, ClearDirty;
@ -88,13 +87,11 @@ module dcache
logic [NUMWAYS-1:0] WayHit; logic [NUMWAYS-1:0] WayHit;
logic CacheHit; logic CacheHit;
logic [BLOCKLEN-1:0] ReadDataBlockM; logic [BLOCKLEN-1:0] ReadDataBlockM;
logic [`XLEN-1:0] ReadDataWordMuxM;
logic [WORDSPERLINE-1:0] SRAMWordEnable; logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SRAMWordWriteEnableM; logic SRAMWordWriteEnableM;
logic SRAMBlockWriteEnableM; logic SRAMBlockWriteEnableM;
logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM;
//logic SRAMWriteEnable;
logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable;
@ -119,11 +116,8 @@ module dcache
logic FlushWayCntRst; logic FlushWayCntRst;
logic VDWriteEnable; logic VDWriteEnable;
logic SelEvict; logic SelEvict;
logic LRUWriteEn; logic LRUWriteEn;
logic [NUMWAYS-1:0] VDWriteEnableWay; logic [NUMWAYS-1:0] VDWriteEnableWay;
// Read Path CPU (IEU) side // Read Path CPU (IEU) side
@ -135,19 +129,11 @@ module dcache
.s(SelAdrM), .s(SelAdrM),
.y(RAdr)); .y(RAdr));
mux2 #(INDEXLEN)
WAdrSelMux(.d0(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(FlushAdr),
.s(&SelAdrM),
.y(WAdr));
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk, MemWay[NUMWAYS-1:0](.clk,
.reset, .reset,
.RAdr, .RAdr,
.WAdr, .WAdr(RAdr), // *** Reduce after addressing in icache also
.PAdr(MemPAdrM), .PAdr(MemPAdrM),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay), .VDWriteEnable(VDWriteEnableWay),
@ -207,7 +193,6 @@ module dcache
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
// Write Path CPU (IEU) side // Write Path CPU (IEU) side
onehotdecoder #(LOGWPL) onehotdecoder #(LOGWPL)
@ -262,44 +247,17 @@ module dcache
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
//assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
// controller // controller
dcachefsm dcachefsm(.clk, dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck,
.reset, .MemRWM, .AtomicM, .CPUBusy, .CacheableM, .IgnoreRequest,
.DCFetchLine, .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM,
.DCWriteLine, .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid,
.BUSACK, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
.MemRWM, .SRAMBlockWriteEnableM, .SelEvict, .SelFlush,
.AtomicM, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.CPUBusy, .FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM,
.CacheableM, .VDWriteEnable, .LRUWriteEn);
.IgnoreRequest,
.CacheHit,
.VictimDirty,
.DCacheStall,
.DCCommittedM,
.DCacheMiss,
.DCacheAccess,
.SelAdrM,
.SetValid,
.ClearValid,
.SetDirty,
.ClearDirty,
.SRAMWordWriteEnableM,
.SRAMBlockWriteEnableM,
.SelEvict,
.SelFlush,
.FlushAdrCntEn,
.FlushWayCntEn,
.FlushAdrCntRst,
.FlushWayCntRst,
.FlushAdrFlag,
.FlushDCacheM,
.VDWriteEnable,
.LRUWriteEn);
endmodule // dcache endmodule // dcache

26
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -38,7 +38,7 @@ module dcachefsm
// hptw inputs // hptw inputs
input logic IgnoreRequest, input logic IgnoreRequest,
// Bus inputs // Bus inputs
input logic BUSACK, input logic DCacheBusAck,
// dcache internals // dcache internals
input logic CacheHit, input logic CacheHit,
input logic VictimDirty, input logic VictimDirty,
@ -50,9 +50,9 @@ module dcachefsm
output logic DCacheMiss, output logic DCacheMiss,
output logic DCacheAccess, output logic DCacheAccess,
// Bus outputs // Bus outputs
output logic DCCommittedM, output logic DCacheCommittedM,
output logic DCWriteLine, output logic DCacheWriteLine,
output logic DCFetchLine, output logic DCacheFetchLine,
// dcache internals // dcache internals
output logic [1:0] SelAdrM, output logic [1:0] SelAdrM,
@ -123,8 +123,8 @@ module dcachefsm
FlushWayCntRst = 1'b0; FlushWayCntRst = 1'b0;
VDWriteEnable = 1'b0; VDWriteEnable = 1'b0;
NextState = STATE_READY; NextState = STATE_READY;
DCFetchLine = 1'b0; DCacheFetchLine = 1'b0;
DCWriteLine = 1'b0; DCacheWriteLine = 1'b0;
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
@ -204,7 +204,7 @@ module dcachefsm
else if((|MemRWM) & CacheableM & ~CacheHit) begin else if((|MemRWM) & CacheableM & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
DCacheStall = 1'b1; DCacheStall = 1'b1;
DCFetchLine = 1'b1; DCacheFetchLine = 1'b1;
end end
else NextState = STATE_READY; else NextState = STATE_READY;
end end
@ -213,7 +213,7 @@ module dcachefsm
DCacheStall = 1'b1; DCacheStall = 1'b1;
SelAdrM = 2'b01; SelAdrM = 2'b01;
if (BUSACK) begin if (DCacheBusAck) begin
NextState = STATE_MISS_FETCH_DONE; NextState = STATE_MISS_FETCH_DONE;
end else begin end else begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
@ -225,7 +225,7 @@ module dcachefsm
SelAdrM = 2'b01; SelAdrM = 2'b01;
if(VictimDirty) begin if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
DCWriteLine = 1'b1; DCacheWriteLine = 1'b1;
end else begin end else begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK; NextState = STATE_MISS_WRITE_CACHE_BLOCK;
end end
@ -299,7 +299,7 @@ module dcachefsm
DCacheStall = 1'b1; DCacheStall = 1'b1;
SelAdrM = 2'b01; SelAdrM = 2'b01;
SelEvict = 1'b1; SelEvict = 1'b1;
if(BUSACK) begin if(DCacheBusAck) begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK; NextState = STATE_MISS_WRITE_CACHE_BLOCK;
end else begin end else begin
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
@ -344,7 +344,7 @@ module dcachefsm
NextState = STATE_FLUSH_WRITE_BACK; NextState = STATE_FLUSH_WRITE_BACK;
FlushAdrCntEn = 1'b0; FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0; FlushWayCntEn = 1'b0;
DCWriteLine = 1'b1; DCacheWriteLine = 1'b1;
end else if (FlushAdrFlag) begin end else if (FlushAdrFlag) begin
NextState = STATE_READY; NextState = STATE_READY;
DCacheStall = 1'b0; DCacheStall = 1'b0;
@ -359,7 +359,7 @@ module dcachefsm
DCacheStall = 1'b1; DCacheStall = 1'b1;
SelAdrM = 2'b10; SelAdrM = 2'b10;
SelFlush = 1'b1; SelFlush = 1'b1;
if(BUSACK) begin if(DCacheBusAck) begin
NextState = STATE_FLUSH_CLEAR_DIRTY; NextState = STATE_FLUSH_CLEAR_DIRTY;
end else begin end else begin
NextState = STATE_FLUSH_WRITE_BACK; NextState = STATE_FLUSH_WRITE_BACK;
@ -391,7 +391,7 @@ module dcachefsm
endcase endcase
end end
assign DCCommittedM = CurrState != STATE_READY; assign DCacheCommittedM = CurrState != STATE_READY;
endmodule // dcachefsm endmodule // dcachefsm

4
wally-pipelined/src/lsu/lrsc.sv
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@ -32,7 +32,7 @@ module lrsc
input logic FlushW, CPUBusy, input logic FlushW, CPUBusy,
input logic MemReadM, input logic MemReadM,
input logic [1:0] LsuRWM, input logic [1:0] LsuRWM,
output logic [1:0] DCRWM, output logic [1:0] DCacheRWM,
input logic [1:0] LsuAtomicM, input logic [1:0] LsuAtomicM,
input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache
output logic SquashSCW output logic SquashSCW
@ -47,7 +47,7 @@ module lrsc
assign scM = LsuRWM[0] && LsuAtomicM[0]; assign scM = LsuRWM[0] && LsuAtomicM[0];
assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign SquashSCM = scM && ~WriteAdrMatchM; assign SquashSCM = scM && ~WriteAdrMatchM;
assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; assign DCacheRWM = SquashSCM ? 2'b00 : LsuRWM;
always_comb begin // ReservationValidM (next value of valid reservation) always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve if (lrM) ReservationValidM = 1; // set valid on load reserve
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc

52
wally-pipelined/src/lsu/lsu.sv
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@ -95,12 +95,12 @@ module lsu
logic DTLBMissM; logic DTLBMissM;
logic DTLBWriteM; logic DTLBWriteM;
logic [1:0] DCRWM; logic [1:0] DCacheRWM;
logic [1:0] LsuRWM; logic [1:0] LsuRWM;
logic [2:0] LsuFunct3M; logic [2:0] LsuFunct3M;
logic [1:0] LsuAtomicM; logic [1:0] LsuAtomicM;
logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr;
logic [11:0] LsuAdrE, DCAdrE; logic [11:0] LsuAdrE, DCacheAdrE;
logic CPUBusy; logic CPUBusy;
logic MemReadM; logic MemReadM;
logic DataMisalignedM; logic DataMisalignedM;
@ -115,7 +115,7 @@ module lsu
logic InterlockStall; logic InterlockStall;
logic IgnoreRequest; logic IgnoreRequest;
logic BusCommittedM, DCCommittedM; logic BusCommittedM, DCacheCommittedM;
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
@ -236,13 +236,13 @@ module lsu
assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1];
assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0];
assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE;
end // if (`MEM_VIRTMEM) end // if (`MEM_VIRTMEM)
else begin else begin
assign InterlockStall = 1'b0; assign InterlockStall = 1'b0;
assign DCAdrE = LsuAdrE; assign DCacheAdrE = LsuAdrE;
assign SelHPTW = 1'b0; assign SelHPTW = 1'b0;
assign IgnoreRequest = 1'b0; assign IgnoreRequest = 1'b0;
@ -263,7 +263,7 @@ module lsu
end end
endgenerate endgenerate
assign CommittedM = SelHPTW | DCCommittedM | BusCommittedM; assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
@ -299,10 +299,10 @@ module lsu
if (`A_SUPPORTED) begin if (`A_SUPPORTED) begin
assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM,
.SquashSCW, .DCRWM); .SquashSCW, .DCacheRWM);
end else begin end else begin
assign SquashSCW = 0; assign SquashSCW = 0;
assign DCRWM = LsuRWM; assign DCacheRWM = LsuRWM;
end end
endgenerate endgenerate
@ -355,9 +355,9 @@ module lsu
logic DCWriteLine; logic DCacheWriteLine;
logic DCFetchLine; logic DCacheFetchLine;
logic BUSACK; logic DCacheBusAck;
logic UnCachedLsuBusRead; logic UnCachedLsuBusRead;
logic UnCachedLsuBusWrite; logic UnCachedLsuBusWrite;
@ -365,23 +365,23 @@ module lsu
dcache dcache(.clk, .reset, .CPUBusy, dcache dcache(.clk, .reset, .CPUBusy,
.MemRWM(DCRWM), .MemRWM(DCacheRWM),
.Funct3M(LsuFunct3M), .Funct3M(LsuFunct3M),
.Funct7M, .FlushDCacheM, .Funct7M, .FlushDCacheM,
.AtomicM(LsuAtomicM), .AtomicM(LsuAtomicM),
.MemAdrE(DCAdrE), .MemAdrE(DCacheAdrE),
.MemPAdrM, .MemPAdrM,
.FinalWriteDataM, .ReadDataWordM, .DCacheStall, .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
.DCacheMiss, .DCacheAccess, .IgnoreRequest, .DCacheMiss, .DCacheAccess, .IgnoreRequest,
.CacheableM(CacheableM), .CacheableM(CacheableM),
.DCCommittedM, .DCacheCommittedM,
.DCacheBusAdr, .DCacheBusAdr,
.ReadDataBlockSetsM, .ReadDataBlockSetsM,
.SelFlush, .SelFlush,
.DCacheMemWriteData, .DCacheMemWriteData,
.DCFetchLine, .DCacheFetchLine,
.DCWriteLine, .DCacheWriteLine,
.BUSACK .DCacheBusAck
); );
@ -475,10 +475,10 @@ module lsu
case(BusCurrState) case(BusCurrState)
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
else if(DCRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(DCacheRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE;
else if(DCRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; else if(DCacheRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ;
else if(DCFetchLine) BusNextState = STATE_BUS_FETCH; else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH;
else if(DCWriteLine) BusNextState = STATE_BUS_WRITE; else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE;
STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
else BusNextState = STATE_BUS_UNCACHED_WRITE; else BusNextState = STATE_BUS_UNCACHED_WRITE;
STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE;
@ -498,24 +498,24 @@ module lsu
assign CntReset = BusCurrState == STATE_BUS_READY; assign CntReset = BusCurrState == STATE_BUS_READY;
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCRWM)) | DCFetchLine | DCWriteLine)) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCacheRWM)) | DCacheFetchLine | DCacheWriteLine)) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_UNCACHED_READ) |
(BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_FETCH) |
(BusCurrState == STATE_BUS_WRITE); (BusCurrState == STATE_BUS_WRITE);
assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCRWM[0])) | assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCacheRWM[0])) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE); (BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE);
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCRWM[1])) | assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCacheRWM[1])) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
assign BUSACK = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign BusCommittedM = BusCurrState != STATE_BUS_READY;
assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCRWM & ~CacheableM)) | assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCacheRWM & ~CacheableM)) |
(BusCurrState == STATE_BUS_UNCACHED_READ | (BusCurrState == STATE_BUS_UNCACHED_READ |
BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE |