clean up repo

fpga/constraints/constraints-ArtyA7.xdc

@@ -71,6 +71,12 @@ set_property PACKAGE_PIN D9 [get_ports {south_reset}]
 set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
 
 
+##### JTAG Port #####
+set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports tck]
+set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports tdo]
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports tms]
+set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports tdi]
+
 
 ##### SD Card I/O #####
 #***** may have to switch to Pmod JB or JC.

fpga/src/fpgaTopArtyA7.sv

@@ -58,7 +58,12 @@ module fpgaTop
    output [0:0]    ddr3_cke,
    output [0:0]    ddr3_cs_n,
    output [1:0]    ddr3_dm,
-   output [0:0]    ddr3_odt
+   output [0:0]    ddr3_odt,
+   // JTAG signals
+   input           tck,
+   input           tdi,
+   input           tms,
+   output          tdo
    );
 
   wire 			   CPUCLK;
@@ -490,7 +495,7 @@ module fpgaTop
   `include "parameter-defs.vh"
 
   wallypipelinedsoc  #(P) 
-  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
+  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .tck, .tdi, .tms, .tdo,
                     .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
                     .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), 
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,

src/debug/dm.sv

@@ -27,7 +27,7 @@
 
 module dm import cvw::*; #(parameter cvw_t P) (
   input  logic                     clk, 
-  input logic 			   rst, // Full hardware reset signal (reset button)
+  input  logic                     rst,
 
   // External JTAG signals
   input  logic                     tck,
@@ -52,7 +52,6 @@ module dm import cvw::*; #(parameter cvw_t P) (
   input  logic                     GPRScanIn,
   output logic                     GPRScanOut
 );
-   
   `include "debug.vh"
 
   // DMI Signals
@@ -78,10 +77,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic                  HaltOnReset;
   logic                  Halted;
 
-   hartcontrol hartcontrol(.clk, .rst(rst | ~DmActive), .NdmReset, .HaltReq,
+  hartcontrol hartcontrol(.clk, .rst(rst || ~DmActive), .NdmReset, .HaltReq,
     .ResumeReq, .HaltOnReset, .DebugStall, .Halted, .AllRunning,
     .AnyRunning, .AllHalted, .AnyHalted, .AllResumeAck, .AnyResumeAck);
 
+
   enum logic [3:0] {INACTIVE, IDLE, ACK, R_DATA, W_DATA, DMSTATUS, W_DMCONTROL, R_DMCONTROL, 
 		    W_ABSTRACTCS, R_ABSTRACTCS, ABST_COMMAND, R_SYSBUSCS, READ_ZERO,
 		    INVALID} State;
@@ -108,7 +108,6 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic [31:0]       Data1Wr;        // Muxed inputs to DataX regs
   logic [31:0]       Data2Wr;        // Muxed inputs to DataX regs
   logic [31:0]       Data3Wr;        // Muxed inputs to DataX regs
-
   // message registers
   logic [31:0] Data0;  // 0x04
   logic [31:0] Data1;  // 0x05
@@ -121,8 +120,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic [31:0] AbstractCS; // 0x16
   logic [31:0] SysBusCS;   // 0x38
 
-   // DM register fields
+  //// DM register fields
-   
   // DMControl
   logic AckUnavail;
   logic DmActive; // This bit is used to (de)activate the DM. Toggling acts as reset
@@ -151,6 +149,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic [2:0] CmdErr;
   const logic [3:0] DataCount = (P.XLEN/32);
 
+
   // Pack registers
   assign DMControl = {2'b0, 1'b0, 2'b0, 1'b0, 10'b0,
     10'b0, 4'b0, NdmReset, DmActive};
@@ -185,7 +184,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
           ConfStrPtrValid <= 0;
           CmdErr <= 0;
           if (ReqValid) begin
-		 if (ReqAddress == `DMCONTROL & ReqOP == `OP_WRITE & ReqData[`DMACTIVE]) begin
+            if (ReqAddress == `DMCONTROL && ReqOP == `OP_WRITE && ReqData[`DMACTIVE]) begin
               DmActive <= ReqData[`DMACTIVE];
               RspOP <= `OP_SUCCESS;
             end
@@ -248,7 +247,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
         W_DMCONTROL : begin
           // While an abstract command is executing (busy in abstractcs is high), a debugger must not change
           // hartsel, and must not write 1 to haltreq, resumereq, ackhavereset, setresethaltreq, or clrresethaltreq
-              if (Busy & (ReqData[`HALTREQ] | ReqData[`RESUMEREQ] | ReqData[`SETRESETHALTREQ] | ReqData[`CLRRESETHALTREQ]))
+          if (Busy && (ReqData[`HALTREQ] || ReqData[`RESUMEREQ] || ReqData[`SETRESETHALTREQ] || ReqData[`CLRRESETHALTREQ]))
             CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
           else begin
             HaltReq <= ReqData[`HALTREQ];
@@ -317,7 +316,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
                 else if (~ReqData[`TRANSFER]); // If not TRANSFER, do nothing
                 else if (InvalidRegNo)
                   CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing
-                      else if (ReqData[`AARWRITE] & RegReadOnly)
+                else if (ReqData[`AARWRITE] && RegReadOnly)
                   CmdErr <= `CMDERR_NOT_SUPPORTED; // If writing to a read only register, set CmdErr, do nothing
                 else begin
                   AcWrite <= ReqData[`AARWRITE];
@@ -353,6 +352,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
     end
   end
 
+
   // Abstract command engine
   // Due to length of the register scan chain,
   // abstract commands execute independently of other DM operations
@@ -374,7 +374,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
 
         AC_SCAN : begin
           if (Cycle == ScanChainLen)
-		AcState <= (GPRRegNo & AcWrite) ? AC_GPRUPDATE : AC_IDLE;
+            AcState <= (GPRRegNo && AcWrite) ? AC_GPRUPDATE : AC_IDLE;
           else
             Cycle <= Cycle + 1;
         end
@@ -391,12 +391,12 @@ module dm import cvw::*; #(parameter cvw_t P) (
   assign DebugGPRUpdate = (AcState == AC_GPRUPDATE);
 
   // Scan Chain
-   assign GPRSel = GPRRegNo & (AcState != AC_IDLE);
+  assign GPRSel = GPRRegNo && (AcState != AC_IDLE);
   assign ScanReg[P.XLEN] = GPRSel ? GPRScanIn : ScanIn;
   assign ScanOut = GPRSel ? 1'b0 : ScanReg[0];
   assign GPRScanOut = GPRSel ? ScanReg[0] : 1'b0;
-   assign ScanEn = ~GPRSel & (AcState == AC_SCAN);
+  assign ScanEn = ~GPRSel && (AcState == AC_SCAN);
-   assign GPRScanEn = GPRSel & (AcState == AC_SCAN);  
+  assign GPRScanEn = GPRSel && (AcState == AC_SCAN);  
   
   // Load data from message registers into scan chain
   if (P.XLEN == 32)
@@ -406,31 +406,32 @@ module dm import cvw::*; #(parameter cvw_t P) (
   else if (P.XLEN == 128)
     assign PackedDataReg = {Data3,Data2,Data1,Data0};
   
-   assign WriteScanReg = AcWrite & (~GPRRegNo & (Cycle == ShiftCount) | GPRRegNo & (Cycle == 0));
+  assign WriteScanReg = AcWrite && (~GPRRegNo && (Cycle == ShiftCount) || GPRRegNo && (Cycle == 0));
   genvar i;
   for (i=0; i<P.XLEN; i=i+1) begin
     // ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain)
-      assign ScanNext[i] = WriteScanReg & ARMask[i] ? PackedDataReg[i] : ScanReg[i+1];
+    assign ScanNext[i] = WriteScanReg && ARMask[i] ? PackedDataReg[i] : ScanReg[i+1];
     flopenr #(1) scanreg (.clk, .reset(rst), .en(AcState == AC_SCAN), .d(ScanNext[i]), .q(ScanReg[i]));
   end
   
   // Message Registers
   assign MaskedScanReg = ARMask & ScanReg[P.XLEN:1];
-   assign WriteMsgReg = (State == W_DATA) & ~Busy;
+  assign WriteMsgReg = (State == W_DATA) && ~Busy;
-   assign StoreScanChain = (AcState == AC_SCAN) & (Cycle == ShiftCount) & ~AcWrite;
+  assign StoreScanChain = (AcState == AC_SCAN) && (Cycle == ShiftCount) && ~AcWrite;
   
   assign Data0Wr = StoreScanChain ? MaskedScanReg[31:0] : ReqData;;
-   flopenr #(32) data0reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA0)), .d(Data0Wr), .q(Data0));
+  flopenr #(32) data0reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA0)), .d(Data0Wr), .q(Data0));
   if (P.XLEN >= 64) begin
     assign Data1Wr = StoreScanChain ?  MaskedScanReg[63:32] : ReqData;
-      flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1));
+    flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1));
   end 
   if (P.XLEN == 128) begin
     assign Data2Wr = StoreScanChain ?  MaskedScanReg[95:64] : ReqData;
     assign Data3Wr = StoreScanChain ?  MaskedScanReg[127:96] : ReqData;
-      flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2));
+    flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2));
-      flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3));
+    flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3));
   end
 
   rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.GPRRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.GPRAddr,.ARMask);
+
 endmodule

src/debug/dtm.sv

@@ -86,6 +86,7 @@ module dtm #(parameter ADDR_WIDTH, parameter JTAG_DEVICE_ID) (
   jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.tck(tcks), .tdi, .tms, .tdo,
     .resetn, .UpdateDtmcs, .DtmcsIn, .DtmcsOut, .CaptureDmi, .UpdateDmi, .DmiIn, .DmiOut);
 
+
   // DTMCS
   assign DtmcsOut = {11'b0, ErrInfo, 3'b0, Idle, DmiStat, ABits, Version};
   always_ff @(posedge clk) begin

src/debug/ir.sv

@@ -49,12 +49,12 @@ module ir (
 
   // Shift register
   always @(posedge clockIR) begin
-    shift_reg[0] <= shift_reg[1] | captureIR;
+    shift_reg[0] <= shift_reg[1] || captureIR;
   end
   genvar i;
   for (i = INST_REG_WIDTH; i > 1; i = i - 1) begin
     always @(posedge clockIR) begin
-      shift_reg[i-1] <= shift_reg[i] & ~captureIR;
+      shift_reg[i-1] <= shift_reg[i] && ~captureIR;
     end
   end
 

src/hazard/hazard.sv

@@ -34,6 +34,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   input  logic FPUStallD,
   input  logic DivBusyE, FDivBusyE,
   input  logic wfiM, IntPendingM,
+  input  logic DebugStall,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,
   output logic FlushD, FlushE, FlushM, FlushW
@@ -89,7 +90,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
   // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
   // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
-  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
+  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | DebugStall;
 
   // Stall each stage for cause or if the next stage is stalled
   // coverage off: StallFCause is always 0
@@ -107,8 +108,9 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   assign LatestUnstalledW = ~StallW & StallM;
   
   // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
-  assign FlushD = LatestUnstalledD | FlushDCause; 
+  // Do not flush if halted for Debug
-  assign FlushE = LatestUnstalledE | FlushECause;
+  assign FlushD = ~DebugStall & (LatestUnstalledD | FlushDCause);
-  assign FlushM = LatestUnstalledM | FlushMCause;
+  assign FlushE = ~DebugStall & (LatestUnstalledE | FlushECause);
-  assign FlushW = LatestUnstalledW | FlushWCause;
+  assign FlushM = ~DebugStall & (LatestUnstalledM | FlushMCause);
+  assign FlushW = ~DebugStall & (LatestUnstalledW | FlushWCause);
 endmodule

src/ieu/controller.sv

@@ -93,7 +93,11 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        CSRWriteFenceM,          // CSR write or fence instruction; needs to flush the following instructions
   output logic [4:0]  RdE, RdM,                // Pipelined destination registers
   // Forwarding controls
-  output logic [4:0]  RdW                      // Register destinations in Execute, Memory, or Writeback stage
+  output logic [4:0]  RdW,                     // Register destinations in Execute, Memory, or Writeback stage
+  // Debug scan chain
+  input  logic        DebugScanEn,
+  input  logic        DebugScanIn,
+  output logic        DebugScanOut
 );
 
   logic [4:0] Rs1E;                      // pipelined register sources
@@ -452,11 +456,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
                           {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
                           {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
   end
-
-  // FIXME: delete once working
-  //flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
-  //                       {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
-  //                       {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
   flopenrc #(5)  RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);  
 
   // Writeback stage pipeline control register

src/ieu/datapath.sv

@@ -89,7 +89,7 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
 
   // Fetch stage signals
   // Decode stage signals
-  logic [4:0]        DB_Rs1D;                        // (Debug) Muxed source register
+  logic [4:0]        Rs1DM;                          // (Debug) Muxed source register
   logic [P.XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
   logic [P.XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
   logic [4:0]        RdD;                            // Destination register in Decode stage
@@ -104,27 +104,29 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   // Writeback stage signals
   logic              RegWriteWM;                     // (Debug) Muxed write enable
   logic [P.XLEN-1:0] SCResultW;                      // Store Conditional result
-  logic [P.XLEN-1:0] ResultW;                        // Result to write to register file
+  logic [P.XLEN-1:0] ResultW;
+  logic [P.XLEN-1:0] ResultWM;              // Result to write to register file
+  logic [4:0]        RdWM;                           // Muxed GPR write address
   logic [P.XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
   logic [P.XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
   logic [P.XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
   // Debug signals
+  logic              DSCR;
   logic [P.XLEN-1:0] DebugGPRWriteD;
 
   // Decode stage
   extend #(P)        ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
+  // Access GPRs from Debug Module
   if (P.DEBUG_SUPPORTED) begin
-    regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, DB_Rs1D, Rs2D, RdWM, ResultWM, R1D, R2D);
+    regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, Rs1DM, Rs2D, RdWM, ResultWM, R1D, R2D);
     assign RegWriteWM = GPRSel ? DebugGPRUpdate : RegWriteW;
-    assign DB_Rs1D = GPRSel ? GPRAddr : Rs1D;
+    assign Rs1DM = GPRSel ? GPRAddr : Rs1D;
     assign RdWM = GPRSel ? GPRAddr : RdW;
     assign ResultWM = GPRSel ? DebugGPRWriteD : ResultW;
     flopenrs #(P.XLEN) GPRScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(GPRScanEn), .scanin(GPRScanIn), .scanout(GPRScanOut));
   end else begin
     regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
   end
-  // FIXME: Delete once working
-  // regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);   
  
   // Execute stage pipeline register and logic
   flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
@@ -147,8 +149,6 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
     flopenrcs #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM, DebugScanEn, DebugScanIn, DebugScanOut);
   else
     flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM);
-  // FIXME: Delete once working 
-  // flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
   
   // Writeback stage pipeline register and logic
   flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);

src/ieu/ieu.sv

@@ -78,7 +78,19 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   output logic              LoadStallD,                      // Structural stalls for load, sent to performance counters
   output logic              StoreStallD,                     // load after store hazard
   output logic              CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
-  output logic              CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
+  output logic              CSRWriteFenceM,                  // CSR write or fence instruction needs to flush subsequent instructions
+  // Debug scan chain
+  input  logic              DebugScanEn,
+  input  logic              DebugScanIn,
+  output logic              DebugScanOut,
+  // GPR debug scan chain
+  input  logic                     GPRSel,
+  input  logic                     DebugCapture,
+  input  logic                     DebugGPRUpdate,
+  input  logic [P.E_SUPPORTED+3:0] GPRAddr,
+  input  logic                     GPRScanEn,
+  input  logic                     GPRScanIn,
+  output logic                     GPRScanOut
 );
 
   logic [2:0] ImmSrcD;                                       // Select type of immediate extension 
@@ -108,6 +120,8 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   logic       BMUActiveE;                                    // Bit manipulation instruction being executed
   logic [1:0] CZeroE;                                        // {czero.nez, czero.eqz} instructions active
 
+  logic DSCR;
+           
   controller #(P) c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, 
@@ -120,7 +134,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
     .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
-    .RdW, .RdE, .RdM);
+    .RdW, .RdE, .RdM, .DebugScanEn, .DebugScanIn, .DebugScanOut(DSCR));
 
   datapath #(P) dp(
     .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
@@ -128,5 +142,6 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
     .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE,
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
-    .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW);             
+    .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut,
+    .GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut);
 endmodule

src/ifu/ifu.sv

@@ -418,11 +418,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     assign InstrM = '0;
     assign DebugScanOut = DSCR;
   end
-
-  // FIXME: delete once working
-  //  flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
-  //end else assign InstrM = '0;
-   
   // PCM is only needed with CSRs or branch prediction
   if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
     if (P.DEBUG_SUPPORTED)
@@ -434,10 +429,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     assign DSCR = DebugScanIn;
   end
   
-  // FIXME: delete once working
-  //  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  //else assign PCM = '0; 
-  
   // If compressed instructions are supported, increment PCLink by 2 or 4 for a jal.  Otherwise, just by 4
   if (P.ZCA_SUPPORTED) begin
     logic CompressedD;  // instruction is compressed

src/lsu/lsu.sv

@@ -160,7 +160,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]     WriteDataZM;
   logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
 
-  logic                  DSCR;                                   // Debug Register Scan In
+  logic                  DSCR;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
@@ -171,9 +171,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR));
   else
     flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM));
-
-  // FIXME: delete once working
-  // flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   if(MISALIGN_SUPPORT) begin : ziccslm_align
     logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, 

src/privileged/csr.sv

@@ -92,7 +92,12 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   //
   output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
   output logic                     IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
-  output logic                     BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
+  output logic                     BigEndianM,                // memory access is big-endian based on privilege mode and STATUS register endian fields
+  // Debug scan chain
+  input  logic                     DebugCapture,
+  input  logic                     DebugScanEn,
+  input  logic                     DebugScanIn,
+  output logic                     DebugScanOut
 );
 
   localparam MIP = 12'h344;
@@ -236,7 +241,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
     .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
-    .MENVCFG_REGW);
+    .MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
 
 
   if (P.S_SUPPORTED) begin:csrs

src/privileged/privileged.sv

@@ -96,7 +96,12 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic              InvalidateICacheM,                              // fence instruction
   output logic              BigEndianM,                                     // Use big endian in current privilege mode
   // Fault outputs                                                         
-  output logic              wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
+  output logic              wfiM, IntPendingM,                              // Stall in Memory stage for WFI until interrupt pending or timeout
+  // Debug scan chain
+  input  logic              DebugCapture,
+  input  logic              DebugScanEn,
+  input  logic              DebugScanIn,
+  output logic              DebugScanOut
 );
 
   logic [3:0]               CauseM;                                         // trap cause
@@ -147,7 +152,8 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
     .EPCM, .TrapVectorM,
-    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
+    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM,
+    .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
 
   // pipeline early-arriving trap sources
   privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,

src/wally/wallypipelinedsoc.sv

@@ -91,7 +91,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
    
   // instantiate processor and internal memories
-  wallypipelinedcore #(P) core(.clk, .reset,
+  wallypipelinedcore #(P) core(.clk, .reset(reset || NdmReset),
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
     .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
@@ -111,12 +111,13 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
             MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; 
   end
 
-  // instantiate debug module (dm)
+  // instantiate debug module
-  if (P.DEBUG_SUPPORTED) begin
+  if (P.DEBUG_SUPPORTED) begin : dm
     dm #(P) dm (.clk, .rst(reset), .NdmReset, .tck, .tdi, .tms, .tdo,
       .DebugStall, .ScanEn, .ScanIn, .ScanOut, .GPRSel, .DebugCapture, .DebugGPRUpdate,
       .GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut);
   end else begin
     assign {NdmReset, DebugStall, ScanOut, GPRSel, DebugCapture, DebugGPRUpdate, GPRAddr, GPRScanEn, GPRScanOut} = '0;
   end
+
 endmodule